UPD78F1502AGK-GAK-AX Datasheet, PDF (635/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 15 SERIAL INTERFACE IICA
(2) Master operation in multi-master system
Figure 15-29. Master Operation in Multi-Master System (1/3)
START
Setting port
IICWL, IICWH ← XXH
Setting of the port used alternatively as the pin to be used.
First, set the port to input mode and the output latch to 0 (see 15.3 (8) Port mode register 6 (PM6)).
Selects a transfer clock.
SVA ← XXH
Sets a local address.
IICF ← 0XH
Setting STCEN and IICRSV
Sets a start condition.
IICCTL0 ← 0XX111XXB
ACKE = WTIM = SPIE = 1
IICCTL0 ← 1XX111XXB
IICE = 1
Setting port
Set the port from input mode to output mode and enable the output of the I²C bus
(see 15.3 (8) Port mode register 6 (PM6)).
Checking bus status^Note
Releases the bus for a specific period.
Bus status is
being checked.
No
INTIICA
interrupt occurs?
STCEN = 1?
No
Yes
Yes
SPD = 1?
No
Yes
Slave operation
SPT = 1
INTIICA
interrupt occurs?
Yes
SPD = 1?
Yes
1
• Waiting to be specified as a slave by other master
• Waiting for a communication start request (depends on user program)
Prepares for starting
communication
(generates a stop condition).
No
Waits for detection
of the stop condition.
No
Slave operation
Master operation
starts?
No
(No communication start request)
Yes
(Communication start request)
SPIE = 0
SPIE = 1
IICRSV = 0?
No
INTIICA
interrupt occurs?
Yes
Slave operation
Yes
A
B
Enables reserving Disables reserving
communication. communication.
No
Waits for a communication request.
Note Confirm that the bus is released (CLD bit = 1, DAD bit = 1) for a specific period (for example, for a period of one
frame). If the SDA0 pin is constantly at low level, decide whether to release the I²C bus (SCL0 and SDA0 pins =
high level) in conformance with the specifications of the product that is communicating.
R01UH0004EJ0501 Rev.5.01
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Jun 20, 2011