UPD78F1502AGK-GAK-AX Datasheet, PDF (981/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
Function
Details of
Function
APPENDIX C LIST OF CAUTIONS
Cautions
(9/39)
Page
X1/XT1
−
When X2 and XT1 are wired in parallel, the crosstalk noise of X2 may increase with p.225 _†
oscillator
XT1, resulting in malfunctioning.
Internal
−
To use the 1, 8, or 20 MHz internal high-speed oscillation clock, use the option byte p.226 _†
high-
to set the frequency in advance (for details, see CHAPTER 26 OPTION BYTE).
speed
Also, the internal high-speed oscillator automatically starts oscillating after reset
oscillator
release. (If 8 MHz or 20 MHz is selected by using the option byte, the microcontroller
operates using the 8 MHz internal high-speed oscillator.) To use the 20 MHz internal
high-speed oscillator to operate the microcontroller, oscillation is started by setting bit
0 (DSCON) of the DSCCTL register to 1 with VDD ≥ 2.7 V.
Clock
When LVI
If the voltage rises with a slope of less than 0.5 V/ms (MIN.) from power application p.229 _†
generator default start
until the voltage reaches 1.8 V, input a low level to the RESET pin from power
operation function stopped application until the voltage reaches 1.8 V, or set the LVI default start function
when
is set (option
stopped by using the option byte (LVIOFF = 0) (see Figure 5-14). By doing so, the
power
byte: LVIOFF = CPU operates with the same timing as <2> and thereafter in Figure 5-13 after reset
supply
1)
release by the RESET pin.
voltage is
It is not necessary to wait for the oscillation stabilization time when an external clock p.229 _†
turned on
input from the EXCLK pin is used.
When LVI
A voltage stabilization time (about 2.12 to 5.84 ms) is required after the supply p.231 _†
default start
voltage reaches 1.61 V (TYP.). If the time for the supply voltage to rise from 1.61 V
function enabled (TYP.) to 2.07 V (TYP.) is shorter than the voltage stabilization time, reset processing
is set (option
is entered after the voltage stabilization time elapses.
byte: LVIOFF = It is not necessary to wait for the oscillation stabilization time when an external clock p.231 _†
0)
input from the EXCLK pin is used.
Controlling X1/P121,
The X1/P121 and X2/EXCLK/P122 pins are in the input port mode after a reset p.232 _†
high-
X2/EXCLK/P122 release.
speed
X1 clock
The CMC register can be written only once after reset release, by an 8-bit memory p.232 _†
system
manipulation instruction. Therefore, it is necessary to also set the value of the
clock
OSCSELS bit at the same time. For OSCSELS bit, see 5.6.3 Example of controlling
subsystem clock.
Set the X1 clock after the supply voltage has reached the operable voltage of the p.232 _†
clock to be used (see CHAPTER 31 ELECTRICAL SPECIFICATIONS).
External main The CMC register can be written only once after reset release, by an 8-bit memory p.233 _†
system clock manipulation instruction. Therefore, it is necessary to also set the value of the
OSCSELS bits at the same time. For OSCSELS bits, see 5.6.3 Example of
controlling subsystem clock.
Set the external main system clock after the supply voltage has reached the operable p.233 _†
voltage of the clock to be used (see CHAPTER 31 ELECTRICAL
SPECIFICATIONS).
High-speed
Be sure to confirm that MCS = 0 or CLS = 1 when setting MSTOP to 1. In addition, p.235 _†
system clock stop peripheral hardware that is operating on the high-speed system clock.
Controlling Internal high- If switching the CPU/peripheral hardware clock from the high-speed system clock to p.236 _†
internal speed oscillation the internal high-speed oscillation clock after restarting the internal high-speed
high-
clock
oscillation clock, do so after 10 μs or more have elapsed.
speed
If the switching is made immediately after the internal high-speed oscillation clock is
oscillation
restarted, the accuracy of the internal high-speed oscillation cannot be guaranteed
clock
for 10 μs.
Be sure to confirm that MCS = 1 or CLS = 1 when setting HIOSTOP to 1. In addition, p.237 _†
stop peripheral hardware that is operating on the internal high-speed oscillation clock.
R01UH0004EJ0501 Rev.5.01
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Jun 20, 2011