UPD78F1502AGK-GAK-AX Datasheet, PDF (559/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 14 SERIAL ARRAY UNIT
14.6.4 LIN reception
Of UART reception, UART3 supports LIN communication.
For LIN reception, channel 3 of unit 1 (SAU1) is used.
UART
Support of LIN communication
Target channel
Pins used
Interrupt
Error interrupt
Error detection flag
Transfer data length
Transfer rate
Data phase
Parity bit
Stop bit
Data direction
UART0
UART1
UART2
UART3
Not supported
Not supported
Not supported
Supported
−
−
−
Channel 3 of SAU1
−
−
−
RxD3
−
−
−
INTSR3
Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.)
−
−
−
INTSRE3
• Framing error detection flag (FEF13)
• Parity error detection flag (PEF13)
• Overrun error detection flag (OVF13)
8 bits
Max. fMCK/6 [bps] (SDRmn [15:9] = 2 or more), Min. fCLK/(2 × 2¹¹ × 128) [bps] ^Note
Forward output (default: high level)
Reverse output (default: low level)
The following selectable
• No parity bit
• Appending 0 parity
• Appending even parity
• Appending odd parity
The following selectable
• Appending 1 bit
• Appending 2 bits
MSB or LSB first
Note Use this operation within a range that satisfies the conditions above and the AC characteristics in the electrical
specifications (see CHAPTER 31 ELECTRICAL SPECIFICATIONS).
Remarks 1. fMCK: Operation clock (MCK) frequency of target channel
fCLK: System clock frequency
2. For 78K0R/LF3, UART0 is not mounted.
Figure 14-84 outlines a reception operation of LIN.
R01UH0004EJ0501 Rev.5.01
543
Jun 20, 2011