UPD78F1502AGK-GAK-AX Datasheet, PDF (610/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 15 SERIAL INTERFACE IICA
Figure 15-9. Format of IICA Control Register 1 (IICCTL1) (2/2)
CLD
Detection of SCL0 pin level (valid only when IICE = 1)
0
The SCL0 pin was detected at low level.
1
The SCL0 pin was detected at high level.
Condition for clearing (CLD = 0)
Condition for setting (CLD = 1)
• When the SCL0 pin is at low level
• When IICE = 0 (operation stop)
• Reset
• When the SCL0 pin is at high level
DAD
Detection of SDA0 pin level (valid only when IICE = 1)
0
The SDA0 pin was detected at low level.
1
The SDA0 pin was detected at high level.
Condition for clearing (DAD = 0)
Condition for setting (DAD = 1)
• When the SDA0 pin is at low level
• When IICE = 0 (operation stop)
• Reset
• When the SDA0 pin is at high level
SMC
0
1
Operates in standard mode.
Operates in fast mode.
Operation mode switching
DFC
Digital filter operation control
0
Digital filter off.
1
Digital filter on.
Digital filter can be used only in fast mode.
In fast mode, the transfer clock does not vary, regardless of the DFC bit being set (1) or cleared (0).
The digital filter is used for noise elimination in fast mode.
Remark IICE: Bit 7 of IICA control register 0 (IICCTL0)
R01UH0004EJ0501 Rev.5.01
594
Jun 20, 2011