UPD78F1502AGK-GAK-AX Datasheet, PDF (550/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 14 SERIAL ARRAY UNIT
(1) Register setting
Figure 14-76. Example of Contents of Registers for UART Reception of UART
(UART0, UART1, UART2, UART3) (1/2)
(a) Serial output register m (SOm)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOm
CKOm2 CKOm1 CKOm0
SOm2 SOm1 SOm0
00001×××00001×××
(b) Serial output enable register m (SOEm) … Sets the bits of the target channel to 0.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOEm
SOEm2 SOEm1 SOEm0
0 0 0 0 0 0 0 0 0 0 0 0 0 × 0/1 ×
(c) Serial channel start register m (SSm) … Sets only the bits of the target channel is 1.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSm
SSm3 SSm2 SSm1 SSm0
0 0 0 0 0 0 0 0 0 0 0 0 0/1 × 0/1 ×
(d) Serial mode register mn (SMRmn)
15 14 13 12 11 10 9 8 7 6 5
SMRmn CKSmn CCSmn
STSmn
SISmn0
0/1 0 0 0 0 0 0 1 0 0/1 1
0: Forward (normal) reception
1: Reverse reception
(e) Serial mode register mr (SMRmr)
15 14 13 12 11 10 9 8 7 6 5
SMRmr CKSmr CCSmr
STSmr
SISmr0
0/1 0 0 0 0 0 0 0 0 0 1
43210
MDmn2 MDmn1 MDmn0
00010
Operation mode of channel n
0: Transfer end interrupt
43210
MDmr2 MDmr1 MDmr0
0 0 0 1 0/1
Same setting value as CKSmn
Operation mode of channel r
0: Transfer end interrupt
1: Buffer empty interrupt
(f) Serial communication operation setting register mn (SCRmn)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCRmn TXEmn RXEmn DAPmn CKPmn
EOCmn PTCmn1 PTCmn0 DIRmn
SLCmn1 SLCmn0
DLSmn2 DLSmn1 DLSmn0
0 1 0 0 0 1 0/1 0/1 0/1 0 0 1 0 1 0/1 0/1
Caution For the UART reception, be sure to set SMRmr of channel r that is to be paired with channel n.
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 1, 3), r: Channel number (r = n − 1),
q: UART number (q = 0 to 3)
: Setting is fixed in the UART reception mode, : Setting disabled (set to the initial value)
×: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
0/1: Set to 0 or 1 depending on the usage of the user
R01UH0004EJ0501 Rev.5.01
534
Jun 20, 2011