UPD78F1502AGK-GAK-AX Datasheet, PDF (836/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 24 LOW-VOLTAGE DETECTOR
Figure 24-9. Timing of Low-Voltage Detector Interrupt Signal Generation
(Bit: LVISEL = 0, Option Byte: LVIOFF = 0)
Supply voltage (VDD)
VLVI value after a change
VLVI = 2.07 V (TYP.)
VPOR = 1.61 V (TYP.)
VPDR = 1.59 V (TYP.)
LVIMK flag
(set by software)
LVISEL flag
(set by software) L
Mask LVI interrupts
(LVIMK = 1)
Change LVI
detection
voltage (VLVI)
Cancelling the
LVI interrupt mask
(LVIMK = 0)
Note 2
<1>
Note 1
<3> Cleared by software
Note 2
LVION flag
(set by software)
Time
LVIF flag
INTLVI
LVIIF flag
LVIMD flag
<2>
(set by software)
Note 3
Cleared by software
Internal reset signal
Notes 1.
2.
3.
The LVIMK flag is set to “1” by reset signal generation.
If LVI operation is disabled when the supply voltage (VDD) is less than or equal to the detection voltage
(VLVI), an interrupt request signal (INTLVI) is generated and LVIIF may be set to 1.
The LVIIF flag may be set when the LVI detection voltage is changed.
Remarks 1. <1> to <3> in Figure 24-9 above correspond to <1> to <3> in the description of “When starting
operation” in 24.4.2 (1) (b) When LVI default start function enabled is set (LVIOFF = 0).
2. VPOR: POC power supply rise detection voltage
VPDR: POC power supply fall detection voltage
R01UH0004EJ0501 Rev.5.01
820
Jun 20, 2011