UPD78F1502AGK-GAK-AX Datasheet, PDF (738/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 18 DMA CONTROLLER
Figure 18-4. Format of DMA Mode Control Register n (DMCn) (2/2)
Address: FFFBAH (DMC0), FFFBBH (DMC1) After reset: 00H R/W
Symbol
<7>
<6>
<5>
<4>
DMCn
STGn
DRSn
DSn
DWAITn
3
IFCn3
2
IFCn2
1
IFCn1
0
IFCn0
IFCn IFCn IFCn IFCn
Selection of DMA start source^Note
3
2
1
0 _{Trigger signal}
Trigger contents
0
0
0
0
−
Disables DMA transfer by interrupt.
(Only software trigger is enabled.)
0
0
1
0 INTTM00
0
0
1
1 INTTM01
0
1
0
0 INTTM04
0
1
0
1 INTTM05
0
1
1
0 INTST0
INTCSI00
0
1
1
1 INTSR0
Timer channel 0 interrupt
Timer channel 1 interrupt
Timer channel 4 interrupt
Timer channel 5 interrupt
UART0 transmission end interrupt
CSI00 transfer end interrupt
UART0 reception end interrupt
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
Other than above
INTCSI01
INTST1
INTCSI10
INTIIC10
INTSR1
INTST3
INTSR3
INTAD
CSI01 transfer end interrupt
UART1 transmission end interrupt
CSI10 transfer end interrupt
IIC10 transfer end interrupt
UART1 reception end interrupt
UART3 transmission end interrupt
UART3 reception end interrupt
A/D conversion end interrupt
Setting prohibited
LF3 LG3 LH3
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
−
√
√
−
√
√
−
√
√
−
−
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
Note The software trigger (STGn) can be used regardless of the IFCn0 to IFCn3 values.
Remarks 1. n: DMA channel number (n = 0, 1)
2. √: Supported, −: Not supported
R01UH0004EJ0501 Rev.5.01
722
Jun 20, 2011