UPD78F1502AGK-GAK-AX Datasheet, PDF (400/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER
(2) Port mode register 3 (PM3)
This register sets port 3 input/output in 1-bit units.
When using the P31/PCLBUZ1/TI00/TO03/RTCDIV/RTCCL/INTP2 and P32/PCLBUZ0/TI01/TO01/INTP5 pins for
clock output/buzzer output, clear PM31 and PM32 and the output latches of P32 and P31 to 0.
PM3 is set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to FFH.
Figure 9-3. Format of Port Mode Register 3 (PM3)
Address: FFF23H After reset: FFH R/W
Symbol
7
6
5
4
PM3
1
1
1
PM34
3
PM33
2
PM32
1
PM31
0
PM30
PM3n
0
1
P3n pin I/O mode selection (n = 0 to 4)
Output mode (output buffer on)
Input mode (output buffer off)
9.4 Operations of Clock Output/Buzzer Output Controller
One pin can be used to output a clock or buzzer sound.
Two output pins, PCLBUZ0 and PCLBUZ1, are available.
PCLBUZ0 outputs a clock/buzzer selected by clock output select register 0 (CKS0).
PCLBUZ1 outputs a clock/buzzer selected by clock output select register 1 (CKS1).
9.4.1 Operation as output pin
PCLBUZn is output as the following procedure.
<1> Select the output frequency with bits 0 to 3 (CCSn0 to CCSn2, CSELn) of the clock output select register (CKSn)
of the PCLBUZn pin (output in disabled status).
<2> Set bit 7 (PCLOEn) of CKSn to 1 to enable clock/buzzer output.
Remark
The controller used for outputting the clock starts or stops outputting the clock one clock after enabling or
disabling clock output (PCLOEn) is switched. At this time, pulses with a narrow width are not output. Figure
9-4 shows enabling or stopping output using PCLOEn and the timing of outputting the clock.
PCLOEn
Figure 9-4. Remote Control Output Application Example
1 clock elapsed
Clock output
Narrow pulses are not recognized
Remark n = 0, 1
R01UH0004EJ0501 Rev.5.01
384
Jun 20, 2011