UPD78F1502AGK-GAK-AX Datasheet, PDF (922/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 31 ELECTRICAL SPECIFICATIONS
(2) Serial interface: Serial array unit (5/18)
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD ≤ 5.5 V, VSS = EVSS = AVss = 0 V)
(d) During communication at same potential (simplified I²C mode)
Parameter
Symbol
Conditions
SCLr clock frequency
fSCL
Hold time when SCLr = “L” tLOW
2.7 V ≤ VDD = EVDD ≤ 5.5 V
Rb = 3 kΩ, Cb = 100 pF
1.8 V ≤ VDD = EVDD ≤ 5.5 V
Rb = 5 kΩ, Cb = 100 pF
2.7 V ≤ VDD = EVDD ≤ 5.5 V
Rb = 3 kΩ, Cb = 100 pF
Hold time when SCLr = “H” tHIGH
Data setup time (reception) tSU:DAT
Data hold time (transmission) tHD:DAT
1.8 V ≤ VDD = EVDD ≤ 5.5 V
Rb = 5 kΩ, Cb = 100 pF
2.7V ≤ VDD = EVDD ≤ 5.5 V
Rb = 3 kΩ, Cb = 100 pF
1.8 V ≤ VDD = EVDD ≤ 5.5 V
Rb = 5 kΩ, Cb = 100 pF
2.7V ≤ VDD = EVDD ≤ 5.5 V
Rb = 3 kΩ, Cb = 100 pF
1.8 V ≤ VDD = EVDD ≤ 5.5 V
Rb = 5 kΩ, Cb = 100 pF
2.7V ≤ VDD = EVDD ≤ 5.5 V
Rb = 3 kΩ, Cb = 100 pF
1.8 V ≤ VDD = EVDD ≤ 5.5 V
Rb = 5 kΩ, Cb = 100 pF
MIN.
1200
MAX.
Unit
400
kHz
300
kHz
ns
1500
ns
1200
ns
1500
ns
1/fMCK+120
ns
1/fMCK+230
ns
0
660
ns
0
710
ns
Caution Select the normal input buffer and the N-ch open drain output (VDD tolerance) mode for SDAr and the
normal output mode for SCLr by using the PIMg and POMx registers.
Remarks 1.
2.
3.
Rb[Ω]:Communication line (SDAr) pull-up resistance,
Cb[F]: Communication line (SCLr, SDAr) load capacitance
r: IIC number (r = 10, 20), g: PIM number (g = 1, 7), x: POM number (x = 1, 7, 8)
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of the SMRmn register. m: Unit number (m = 0, 1),
n: Channel number (n = 0, 2), mn = 02, 10)
R01UH0004EJ0501 Rev.5.01
906
Jun 20, 2011