UPD78F1502AGK-GAK-AX Datasheet, PDF (280/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 6 TIMER ARRAY UNIT
(3) Timer mode register mn (TMRmn)
TMRmn sets an operation mode of channel n of timer array unit m. It is used to select an operation clock (MCK), a
count clock, whether the timer operates as the master or a slave, a start trigger and a capture trigger, the valid
edge of the timer input, and an operation mode (interval, capture, event counter, one-count, or capture & one-
count).
Rewriting TMRmn is prohibited when the register is in operation (when TEm = 1). However, bits 7 and 6 (CISmn1,
CISmn0) can be rewritten even while the register is operating with some functions (when TEm = 1) (for details, see
6.7 Operation of Timer Array Unit as Independent Channel and 6.8 Operation of Plural Channels of Timer
Array Unit).
TMRmn can be set by a 16-bit memory manipulation instruction.
Reset signal generation clears this register to 0000H.
Figure 6-7. Format of Timer Mode Register mn (TMRmn) (1/4)
Address: F0190H, F0191H (TMR00) to F019EH, F019FH (TMR07) After reset: 0000H R/W
F01C8H, F01C9H (TMR10) to F01CEH, F01CFH (TMR13)
Symbol
15 14 13 12 11 10 9
8
7
6
5
4
TMRmn CKS 0
0 CCS MAST STS STS STS CIS CIS 0
0
mn
mn ERmn mn2 mn1 mn0 mn1 mn0
3
2
1
0
MD MD MD MD
mn3 mn2 mn1 mn0
CKS
mn
Selection of operation clock (MCK) of channel n
0 Operation clock CKm0 set by TPSm register
1 Operation clock CKm1 set by TPSm register
Operation clock MCK is used by the edge detector. A count clock (TCLK) and a sampling clock are generated
depending on the setting of the CCSmn bit.
CCS
mn
Selection of count clock (TCLK) of channel n
0 Operation clock MCK specified by CKSmn bit
1 Valid edge of input signal input from TIpq pin, fSUB/2, fSUB/4, or INTRTC1 (the timer input used with channel x
is selected by using TISm register).
Count clock TCLK is used for the timer/counter, output controller, and interrupt controller.
If CCSmn = 1, use the count clock under the following condition.
• The frequency of the operating clock selected by using CKSmn ≥ The frequency of the clock selected by using
TISmn × 2
Caution Be sure to clear bits 14, 13, 5, and 4 to “0”.
Remark
mn: Unit number + Channel number, pq: Unit number + Channel number (only for channels provided with
timer I/O pins)
78K0R/LF3: m = 0, 1, mn = 00 to 07, 10 to 13, pq = 00 to 04, 07
78K0R/LG3: m = 0, 1, mn = 00 to 07, 10 to 13, pq = 00 to 07
78K0R/LH3: m = 0, 1, mn = 00 to 07, 10 to 13, pq = 00 to 07, 10 to 13
R01UH0004EJ0501 Rev.5.01
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Jun 20, 2011