UPD78F1502AGK-GAK-AX Datasheet, PDF (273/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 6 TIMER ARRAY UNIT
Figure 6-2. Block Diagram of Timer Array Unit 1
Peripheral enable
register 0 TAU1EN
(PER0)
Timer clock select register 1 (TPS1)
PRS113 PRS112PRS111 PRS110 PRS103 PRS102PRS101 PRS100
4
4
fCLK
Prescaler
fCLK/2⁰ to fCLK/2¹⁵
fCLK/2⁰ to fCLK/2¹⁵
Selector
Selector
Timer channel
TE13 TE12 TE11 TE10 enable status
register 1 (TE1)
Timer channel
TS13 TS12 TS11 TS10 ^{start register 1}
(TS1)
Timer channel
TT13 TT12 TT11 TT10 ^{stop register 1}
(TT1)
Timer input
TIS13 TIS12 TIS11 TIS10 select register 1
(TIS1)
TNFEN TNFEN TNFEN TNFEN
Noise filter
enable register 2
13
12
11
10 _(NFEN2)
Timer output
TOE13 TOE12 TOE11 TOE10 ^{enable register 1}
(TOE1)
Timer output
TO13 TO12 TO11 TO10 register 1
(TO1)
Timer output
TOM13 TOM12 TOM11 TOM10 mode register 1
(TOM1)
Timer output
TOL13 TOL12 TOL11 TOL10 level register 1
(TOL1)
TI10
fSUBC/2
TI11
(Timer
input pin)
Channel 0
CK10
CK11
MCK
Edge
detection
Slave/master
controller
Trigger signal to slave channel
Clock signal to slave channel
Interrupt signal to slave channel
TCLK ^{Timer controller}
Mode
selection
Output
controller
Interrupt
controller
Output latch
(P85)
PM85
TIS11
TNFEN11
Channel 1
Slave/master
controller
Timer counter register 11 (TCR11)
Timer data register 11 (TDR11)
Timer status
register 11 (TSR11)
OVF
Overflow 11
CKS11
CCS11
MAS
TER11
STS112 STS111 STS110 CIS111 CIS110
MD113
MD112
MD111 MD110
Timer mode register 11 (TMR11)
TI12
Channel 2
TI13
Channel 3
TO10
INTTM10
TO11
(Timer
output pin)
INTTM11
(Timer
interrupt)
TO12
INTTM12
TO13
INTTM13
Remark For the channels 0 to 3 of 78K0R/LF3 and 78K0R/LG3, the timer I/O pins (TI10/TO10 to TI13/TO13) are not
mounted.
R01UH0004EJ0501 Rev.5.01
257
Jun 20, 2011