UPD78F1502AGK-GAK-AX Datasheet, PDF (663/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 15 SERIAL INTERFACE IICA
Figure 15-32. Example of Master to Slave Communication
(When 9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (1/4)
(1) Start condition ~ address ~ data
Master side
IICA
ACKD
(ACK detection)
WTIM
(8 or 9 clock wait) ^H
ACKE
(ACK control)
H
MSTS
(communication status)
STT
(ST trigger)
<1>
SPT
(SP trigger)
L
WREL
(wait cancellation)
L
INTIICA
(interrupt)
TRC
(transmit/receive)
Bus line
SCL0 (bus)
(clock line)
SDA0 (bus)
(data line)
Slave side
IICA
ACKD
(ACK detection)
STD
(ST detection)
SPD
(SP detection)
WTIM
(8 or 9 clock wait) ^H
ACKE
(ACK control)
H
MSTS
(communication status) ^L
WREL
(wait cancellation)
INTIICA
(interrupt)
TRC
(transmit/receive) ^L
<2>
Note 2
Start condition
AD6 AD5 AD4 AD3 AD2 AD1 AD0
Slave address
Note 1
<5>
<4>
W _ACK
D17
<3>
<6> ^{Note 3}
: Wait state by slave device
: Wait state by master and slave devices
Notes 1. Write data to IICA, not setting the WREL bit, in order to cancel a wait state during master transmission.
2. Make sure that the time between the fall of the SDA0 pin signal and the fall of the SCL0 pin signal is at
least 4.0 μs when specifying standard mode and at least 0.6 μs when specifying fast mode.
3. To cancel slave wait, write “FFH” to IICA or set the WREL bit.
R01UH0004EJ0501 Rev.5.01
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Jun 20, 2011