UPD78F1502AGK-GAK-AX Datasheet, PDF (395/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 8 WATCHDOG TIMER
8.4.3 Setting window open period of watchdog timer
Set the window open period of the watchdog timer by using bits 6 and 5 (WINDOW1, WINDOW0) of the option byte
(000C0H). The outline of the window is as follows.
• If “ACH” is written to WDTE during the window open period, the watchdog timer is cleared and starts counting again.
• Even if “ACH” is written to WDTE during the window close period, an abnormality is detected and an internal reset
signal is generated.
Example: If the window open period is 50%
Counting
starts
Window close period (50%)
Overflow
time
Window close period (50%)
Internal reset signal is generated
if "ACH" is written to WDTE.
Counting starts again when
"ACH" is written to WDTE.
Caution When data is written to WDTE for the first time after reset release, the watchdog timer is cleared in
any timing regardless of the window open time, as long as the register is written before the overflow
time, and the watchdog timer starts counting again.
The window open period to be set is as follows.
Table 8-4. Setting Window Open Period of Watchdog Timer
WINDOW1
0
0
1
1
WINDOW0
0
1
0
1
Window Open Period of Watchdog Timer
Setting prohibited
50%
75%
100%
Cautions 1. The watchdog timer continues its operation during self-programming of the flash memory and
EEPROM emulation. During processing, the interrupt acknowledge time is delayed. Set the
overflow time and window size taking this delay into consideration.
2. When bit 0 (WDSTBYON) of the option byte (000C0H) = 0, the window open period is 100%
regardless of the values of WINDOW1 and WINDOW0.
R01UH0004EJ0501 Rev.5.01
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Jun 20, 2011