UPD78F1502AGK-GAK-AX Datasheet, PDF (846/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 26 OPTION BYTE
26.1.2 On-chip debug option byte (000C3H/ 010C3H)
{ Control of on-chip debug operation
• On-chip debug operation is disabled or enabled.
{ Handling of data of flash memory in case of failure in on-chip debug security ID authentication
• Data of flash memory is erased or not erased in case of failure in on-chip debug security ID
authentication.
Caution Set the same value as 000C3H to 010C3H when the boot swap operation is used because
000C3H is replaced by 010C3H.
26.2 Format of User Option Byte
The format of user option byte is shown below.
Figure 26-1. Format of User Option Byte (000C0H/010C0H) (1/2)
Address: 000C0H/010C0H^{Note 1}
7
6
WDTINIT WINDOW1
5
WINDOW0
4
WDTON
3
WDCS2
2
WDCS1
1
WDCS0
0
WDSTBYON
WDTINIT
0
1
Use of interval interrupt of watchdog timer
Interval interrupt is not used.
Interval interrupt is generated when 75% of the overflow time is reached.
WINDOW1
0
0
1
1
WINDOW0
0
1
0
1
Setting prohibited
50%
75%
100%
Watchdog timer window open period^{Note 2}
WDTON
0
1
Operation control of watchdog timer counter
Counter operation disabled (counting stopped after reset)
Counter operation enabled (counting started after reset)
WDCS2
0
0
0
0
1
1
1
1
WDCS1
0
0
1
1
0
0
1
1
WDCS0
0
1
0
1
0
1
0
1
Watchdog timer overflow time
(fIL = 33 kHz (MAX.))
2⁷/fIL (3.88 ms)
2⁸/fIL (7.76 ms)
2⁹/fIL (15.52 ms)
2¹⁰/fIL (31.03 ms)
2¹²/fIL (124.12 ms)
2¹⁴/fIL (496.48 ms)
2¹⁵/fIL (992.97 ms)
2¹⁷/fIL (3971.88 ms)
R01UH0004EJ0501 Rev.5.01
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Jun 20, 2011