UPD78F1502AGK-GAK-AX Datasheet, PDF (879/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 30 INSTRUCTION SET
Table 30-5. Operation List (4/17)
Instruction Mnemonic
Group
Operands
Bytes
Clocks
Note 1 Note 2
Operation
Flag
Z AC CY
8-bit data XCH
transfer
A, ES:!addr16
A, ES:[DE]
5
3
− A ←→ (ES, addr16)
3
3
− A ←→ (ES, DE)
A, ES:[DE + byte]
4
3
− A ←→ ((ES, DE) + byte)
A, ES:[HL]
3
3
− A ←→ (ES, HL)
A, ES:[HL + byte]
4
3
− A ←→ ((ES, HL) + byte)
A, ES:[HL + B]
3
3
− A ←→ ((ES, HL) + B)
A, ES:[HL + C]
3
3
− A ←→ ((ES, HL) + C)
ONEB A
1
1
− A ← 01H
X
1
1
− X ← 01H
B
1
1
− B ← 01H
C
1
1
− C ← 01H
saddr
2
1
− (saddr) ← 01H
!addr16
3
1
− (addr16) ← 01H
ES:!addr16
4
2
− (ES, addr16) ← 01H
CLRB
A
1
1
− A ← 00H
X
1
1
− X ← 00H
B
1
1
− B ← 00H
C
1
1
− C ← 00H
saddr
2
1
− (saddr) ← 00H
!addr16
3
1
− (addr16) ← 00H
ES:!addr16
4
2
− (ES,addr16) ← 00H
MOVS [HL + byte], X
3
1
− (HL + byte) ← X
×
×
ES:[HL + byte], X
4
2
− (ES, HL + byte) ← X
×
×
16-bit
data
transfer
MOVW
rp, #word
saddrp, #word
sfrp, #word
3
1
− rp ← word
4
1
− (saddrp) ← word
4
1
− sfrp ← word
AX, saddrp
2
1
− AX ← (saddrp)
saddrp, AX
2
1
− (saddrp) ← AX
AX, sfrp
2
1
− AX ← sfrp
sfrp, AX
AX, rp
rp, AX
2
Note 3
1
Note 3
1
1
− sfrp ← AX
1
− AX ← rp
1
− rp ← AX
Notes 1.
2.
3.
When the internal RAM area or SFR area is accessed, or for an instruction with no data access.
When the program memory area is accessed.
Except rp = AX
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the system clock control
register (CKC).
2. This number of clocks is for when the program is in the internal ROM (flash memory) area.
R01UH0004EJ0501 Rev.5.01
863
Jun 20, 2011