UPD78F1502AGK-GAK-AX Datasheet, PDF (755/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 18 DMA CONTROLLER
(3) Operation in standby mode
The DMA controller operates as follows in the standby mode.
Status
HALT mode
STOP mode
Table 18-3. DMA Operation in Standby Mode
DMA Operation
Normal operation
Stops operation.
If DMA transfer and STOP instruction execution contend, DMA transfer may be
damaged. Therefore, stop DMA before executing the STOP instruction.
(4) DMA pending instruction
Even if a DMA request is generated, DMA transfer is held pending immediately after the following instructions.
• CALL !addr16
<R>
• CALL $!addr20
• CALL !!addr20
• CALL rp
• CALLT [addr5]
• BRK
<R>
• Bit manipulation instructions for registers IF0L, IF0H, IF1L, IF1H, IF2L, IF2H, MK0L, MK0H, MK1L, MK1H,
MK2L, MK2H, PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR10L, PR10H, PR11L, PR11H, PR12L,
PR12H and PSW each.
(5) Operation if address in general-purpose register area or other than those of internal RAM area is specified
The address indicated by DRA0n is incremented during DMA transfer. If the address is incremented to an
address in the general-purpose register area or exceeds the area of the internal RAM, the following operation is
performed.
z In mode of transfer from SFR to RAM
The data of that address is lost.
z In mode of transfer from RAM to SFR
Undefined data is transferred to SFR.
In either case, malfunctioning may occur or damage may be done to the system. Therefore, make sure that the
address is within the internal RAM area other than the general-purpose register area.
FFF00H
FFEFFH
FFEE0H
FFEDFH
General-purpose registers
Internal RAM
DMA transfer enabled area
R01UH0004EJ0501 Rev.5.01
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Jun 20, 2011