UPD78F1502AGK-GAK-AX Datasheet, PDF (943/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 31 ELECTRICAL SPECIFICATIONS
LCD Characteristics (3/4)
(2) Internal voltage boosting method (2/2)
(b) 1/4 bias method (TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
LCD output voltage variation range VLCD3
C1 to C5^{Note 1}
= 0.47 μF^{Note 2}
VLCD = 00H^{Note 5}
VLCD = 01H^{Note 5}
1.67
1.62
1.75
1.70
VLCD = 02H^{Note 5}
1.57
1.65
VLCD = 03H^{Note 5}
1.52
1.60
VLCD = 04H^{Note 5}
1.47
1.55
VLCD = 05H^{Note 5}
1.42
1.50
VLCD = 06H^{Note 5}
1.37
1.45
VLCD = 07H^{Note 5}
1.32
1.40
VLCD = 08H^{Note 5}
1.27
1.35
MAX.
Unit
1.83
V
1.78
V
1.73
V
1.68
V
1.63
V
1.58
V
1.53
V
1.48
V
1.43
V
VLCD = 09H
1.22
1.30
1.375
V
VLCD = 0AH
1.17
1.25
1.33
V
VLCD = 0BH
1.12
1.20
1.28
V
VLCD = 0CH
1.07
1.15
1.23
V
VLCD = 0DH
1.02
1.10
1.18
V
VLCD = 0EH
0.97
1.05
1.13
V
VLCD = 0FH
0.92
1.00
1.08
V
VLCD = 10H
0.87
0.95
1.03
V
VLCD = 11H
0.82
0.90
0.98
V
VLCD = 12H
0.77
0.85
0.93
V
VLCD = 13H
0.72
0.80
0.88
V
Doubler output voltage
VLCD2
C1 to C5^{Note 1} = 0.47 μF
2 VLCD3−0.08 2 VLCD3
2 VLCD3
V
Tripler output voltage
VLCD1
C1 to C5^{Note 1} = 0.47 μF
3 VLCD3−0.12 3 VLCD3
3 VLCD3
V
Quadruply output voltage
VLCD0
C1 to C5^{Note 1} = 0.47 μF
4 VLCD3−0.16 4 VLCD3
4 VLCD3
V
Reference voltage setup time ^{Note 2} tVAWAIT2
2
ms
Voltage boost wait time^{Note 3}
tVAWAIT1
500
ms
VDD > VLC0
5
s
LCD output resistor^{Note 4} (Common) RODC
IO = ±5 μA
40
kΩ
LCD output resistor^{Note 4} (Segment) ROCS
IO = ±1 μA
200
kΩ
Notes 1. This is a capacitor that is connected between voltage pins used to drive the LCD.
C1: A capacitor connected between CAPH and CAPL
C2: A capacitor connected between VLC0 and GND
C3: A capacitor connected between VLC1 and GND
C4: A capacitor connected between VLC2 and GND
C5: A capacitor connected between VLC3 and GND
C1 = C2 = C3 = C4 = C5 = 0.47 pF±30 %
2. This is the required wait time from when the reference voltage is specified by using the LVCD register (or the
register is reset to use the default value of the reference voltage) until voltage boosting is started (VLCON = 1).
3. This is the wait time from when voltage boosting is started (VLCON = 1) until display is enabled (LCDON = 1).
4. The output resistor is a resistor connected between one of the VLC0, VLC1, VLC2, VLC3 and VSS pins, and either of
the SEG and COM pins.
5. These settings are prohibited because VLC0 > 5.5 V.
R01UH0004EJ0501 Rev.5.01
927
Jun 20, 2011