UPD78F1502AGK-GAK-AX Datasheet, PDF (757/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 19 INTERRUPT FUNCTIONS
19.2 Interrupt Sources and Configuration
The interrupt sources consist of maskable interrupts and software interrupts. In addition, they also have up to five reset
sources (see Table 19-1). The vector codes that store the program start address when branching due to the generation of
a reset or various interrupt requests are two bytes each, so interrupts jump to a 64 K address of 00000H to 0FFFFH.
Table 19-1. Interrupt Source List (1/3)
Interrupt
Type
Internal/
External
Basic
Configuration
Type
Note 1
Default
Priority^{Note 2}
Name
Interrupt Source
Trigger
Vector LF LG LH
Table 3 3 3
Address
Maskable Internal
(A)
External
(B)
Internal
(A)
0
INTWDTI Watchdog timer interval^{Note 3}
(75% of overflow time)
00004H √ √ √
1
INTLVI
Low-voltage detection^{Note 4}
00006H √ √ √
2
INTP0
Pin input edge detection
00008H √ √ √
3
INTP1
0000AH √ √ √
4
INTP2
0000CH √ √ √
5
INTP3
0000EH √ √ √
6
INTP4
00010H √ √ √
7
INTP5
00012H √ √ √
8
INTST3 End of UART3 transmission
00014H √ √ √
9
INTSR3 End of UART3 reception
00016H √ √ √
10
INTSRE3 UART3 reception error occurrence
00018H √ √ √
11
INTDMA0 End of DMA0 transfer
0001AH √ √ √
12
INTDMA1 End of DMA1 transfer
0001CH √ √ √
13
INTST0 End of UART0 transmission
0001EH − √ √
INTCSI00 End of CSI00 communication
−√√
14
INTSR0 End of UART0 reception
00020H − √ √
INTCSI01 End of CSI01 communication
−−√
15
INTSRE0 CSI01/UART0 reception error occurrence 00022H √ √ √
16
INTST1 End of UART1 transmission
00024H √ √ √
INTCSI10 End of CSI10 communication
√√√
INTIIC10 End of IIC10 communication
√√√
17
INTSR1 End of UART1 reception
00026H √ √ √
18
INTSRE1 UART1 reception error occurrence
00028H √ √ √
19
INTIICA End of IICA communication
0002AH − √ √
20
INTTM00 End of timer channel 0 count or capture 0002CH √ √ √
Notes 1.
2.
3.
4.
The default priority determines the sequence of interrupts if two or more maskable interrupts occur
simultaneously. Zero indicates the highest priority and 45 indicates the lowest priority.
Basic configuration types (A) to (D) correspond to (A) to (D) in Figure 19-1.
When bit 7 (WDTINT) of the option byte (000C0H) is set to 1.
When bit 1 (LVIMD) of the low-voltage detection register (LVIM) is cleared to 0.
R01UH0004EJ0501 Rev.5.01
741
Jun 20, 2011