UPD78F1502AGK-GAK-AX Datasheet, PDF (266/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 5 CLOCK GENERATOR
Table 5-9. Maximum Number of Clocks Required in fMAINC ↔fSUBC
Set Value Before Switchover
CSS
0
(fCLK = fMAINC)
1
(fCLK = fSUBC)
fMAINC>fSUBC
fMAINC>fSUBC
Set Value After Switchover
CSS
0
1
(fCLK = fMAINC)
(fCLK = fSUBC)
1 + 2fMAINC/fSUBC clock
2 + fSUBC/fMAINC clock
Remarks 1. The number of clocks listed in Table 5-7 to Table 5-9 is the number of CPU clocks before switchover.
2. Calculate the number of clocks in Table 5-7 to Table 5-9 by removing the decimal portion.
Example When switching the main system clock from the internal high-speed oscillation clock to the
high-speed system clock (@ oscillation with fIH = 8 MHz, fMX = 10 MHz)
1 + fIH/fMX = 1 + 8/10 = 1 + 0.8 = 1.8 → 2 clocks
5.6.8 Conditions before clock oscillation is stopped
The following lists the register flag settings for stopping the clock oscillation (disabling external clock input) and
conditions before the clock oscillation is stopped.
Table 5-10. Conditions Before the Clock Oscillation Is Stopped and Flag Settings
Clock
Internal high-speed
oscillation clock
X1 clock
External main system clock
Subsystem clock
20 MHz internal high-speed
oscillation clock
Conditions Before Clock Oscillation Is Stopped
(External Clock Input Disabled)
MCS = 1 or CLS = 1
(The CPU is operating on a clock other than the internal high-speed
oscillation clock)
MCS = 0 or CLS = 1
(The CPU is operating on a clock other than the high-speed system clock)
CLS = 0
(The CPU is operating on a clock other than the subsystem clock)
SELDSC = 0
(The main system clock is operating on a clock other than the 20 MHz
internal high-speed oscillation clock.)
Flag Settings of SFR
Register
HIOSTOP = 1
MSTOP = 1
XTSTOP = 1
DSCON = 0
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Jun 20, 2011