UPD78F1502AGK-GAK-AX Datasheet, PDF (579/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 14 SERIAL ARRAY UNIT
(2) Processing flow
Figure 14-96. Timing Chart of Data Reception
(a) When starting data reception
SSmn
STmn
SEmn
SOEmn _{“H”}
TXEmn,
RXEmn
TXEmn = 1 / RXEmn = 0
SDRmn
SCLr output
SDAr output
SDAr input
Shift
register mn
INTIICr
TSFmn
TXEmn = 0 / RXEmn = 1
Dummy data (FFH)
Receive data
ACK
D7 D6 D5 D4 D3 D2 D1 D0
Shift operation
(b) When receiving last data
STmn
SEmn
SOEmn
TXEmn,
RXEmn
SDRmn
Output is enabled by serial
communication operation
Dummy data (FFH) Receive data
SCLr output
SDAr output
ACK
SDAr input D2 D1 D0
D7
Shift
register mn
INTIICr
TSFmn
Shift operation
Output is stopped by serial communication operation
TXEmn = 0 / RXEmn = 1
Dummy data (FFH)
NACK
D6 D5 D4 D3 D2 D1 D0
Shift operation
Receive data
Reception of last byte
SOmn bit SOmn bit
manipulation manipulation
IIC operation stop CKOmn bit
manipulation
Stop condition
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), r: IIC number (r = 10, 20)
R01UH0004EJ0501 Rev.5.01
563
Jun 20, 2011