UPD78F1502AGK-GAK-AX Datasheet, PDF (784/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 19 INTERRUPT FUNCTIONS
Figure 19-17. Examples of Multiple Interrupt Servicing (1/2)
Example 1. Multiple interrupt servicing occurs twice
Main processing
INTxx servicing
INTyy servicing
INTzz servicing
EI
INTxx
(PR = 11)
IE = 0
EI
INTyy
(PR = 10)
IE = 0
EI
INTzz
(PR = 01)
IE = 0
IE = 1
RETI IE = 1
RETI
IE = 1
RETI
During servicing of interrupt INTxx, two interrupt requests, INTyy and INTzz, are acknowledged, and multiple interrupt
servicing takes place. Before each interrupt request is acknowledged, the EI instruction must always be issued to enable
interrupt request acknowledgment.
Example 2. Multiple interrupt servicing does not occur due to priority control
Main processing
INTxx servicing INTyy servicing
EI
INTxx
(PR = 10)
IE = 0
EI
INTyy
(PR = 11)
IE = 1
RETI
1 instruction execution
IE = 0
IE = 1
RETI
Interrupt request INTyy issued during servicing of interrupt INTxx is not acknowledged because its priority is lower than
that of INTxx, and multiple interrupt servicing does not take place. The INTyy interrupt request is held pending, and is
acknowledged following execution of one main processing instruction.
PR = 00: Specify level 0 with ××PR1× = 0, ××PR0× = 0 (higher priority level)
PR = 01: Specify level 1 with ××PR1× = 0, ××PR0× = 1
PR = 10: Specify level 2 with ××PR1× = 1, ××PR0× = 0
PR = 11: Specify level 1 with ××PR1× = 1, ××PR0× = 1 (lower priority level)
IE = 0: Interrupt request acknowledgment is disabled
IE = 1: Interrupt request acknowledgment is enabled.
R01UH0004EJ0501 Rev.5.01
768
Jun 20, 2011