UPD78F1502AGK-GAK-AX Datasheet, PDF (988/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
Function
Details of
Function
APPENDIX C LIST OF CAUTIONS
Cautions
(16/39)
Page
Watchdog
timer
Clock
output/
buzzer
output
controller
A/D
converter
Setting interval When operating with the X1 oscillation clock after releasing the STOP mode, the
p.380 _†
interrupt
CPU starts operating after the oscillation stabilization time has elapsed.
Therefore, if the period between the STOP mode release and the watchdog timer
overflow is short, an overflow occurs during the oscillation stabilization time, causing
a reset.
Consequently, set the overflow time in consideration of the oscillation stabilization
time when operating with the X1 oscillation clock and when the watchdog timer is to
be cleared after the STOP mode release by an interval interrupt.
CKSn: Clock
Change the output clock after disabling clock output (PCLOEn = 0).
p.383 _†
output select
If the selected clock (fMAIN or fSUB) stops during clock output (PCLOEn = 1), the output p.383 _†
registers n
becomes undefined.
To shift to STOP mode when the main system clock is selected (CSELn = 0), set p.383 _†
PCLOEn = 0 before executing the STOP instruction. When the subsystem clock is
selected (CSELn = 1), PCLOEn = 1 can be set because the clock can be output in
STOP mode.
PER0:
When setting the A/D converter, be sure to set ADCEN to 1 first. If ADCEN = 0, p.390 _†
Peripheral
writing to a control register of the A/D converter is ignored, and, even if the register is
enable register 0 read, only the default value is read.
ADM: A/D
A/D conversion must be stopped before rewriting bits ADSCM, FR0 to FR2, LV1, and p.392 _†
converter mode LV0 to values other than the identical data.
register
When using the A/D converter in normal mode 2 (LV1 = 0, LV0 = 1) or low voltage pp.392 _†
mode (LV1 = 1, LV0 = 0), enable the input gate voltage boost circuit for the A/D , 393
converter by using the analog reference voltage control register (ADVRC), and then
set ADCE and ADCS to 1. After the voltage boost circuit stabilization time (10 μs)
passes after the input gate voltage boost circuit for the A/D converter has been
enabled, set ADCS to 1.
ADM1: A/D
Rewriting ADM1 during A/D conversion is prohibited. Rewrite it when conversion
p.394 _†
converter mode operation is stopped (ADCS = 0).
register 1
ADVRC: Analog When using the A/D converter in normal mode 2 (LV1 = 0, LV0 = 1) or low voltage p.395 _†
reference
mode (LV1 = 1, LV0 = 0), enable the input gate voltage boost circuit for the A/D
voltage control converter by using the analog reference voltage control register (ADVRC), and then
register
set ADCE and ADCS to 1. After the voltage boost circuit stabilization time (10 μs)
passes after the input gate voltage boost circuit for the A/D converter has been
enabled, set ADCS to 1.
To use voltage reference output to the positive reference voltage of the A/D
p.396 _†
converter, be sure to set VRON to 1 after setting VRSEL to 1.
Do not change the output voltage of the reference voltage by using VRGV during the p.396 _†
voltage reference operation (VRON = 1).
ADCR: 12-bit When writing to A/D converter mode register (ADM), analog input channel p.396 _†
A/D conversion specification register (ADS), and A/D port configuration register (ADPC), the contents
result register of ADCR may become undefined. Read the conversion result following conversion
completion before writing to ADM, ADS, and ADPC. Using timing other than the
above may cause an incorrect conversion result to be read.
ADCRH: 8-bit When writing to A/D converter mode register (ADM), analog input channel p.397 _†
A/D conversion specification register (ADS), and A/D port configuration register (ADPC), the contents
result register of ADCRH may become undefined. Read the conversion result following conversion
completion before writing to ADM, ADS, and ADPC. Using timing other than the
above may cause an incorrect conversion result to be read.
R01UH0004EJ0501 Rev.5.01
972
Jun 20, 2011