UPD78F1502AGK-GAK-AX Datasheet, PDF (252/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 5 CLOCK GENERATOR
<2> Setting the internal high-speed oscillation clock as the source clock of the CPU/peripheral hardware clock
and setting the division ratio of the set clock (CKC register)
MCM0
0
MDIV2
0
0
0
0
1
1
MDIV1
0
0
1
1
0
0
MDIV0
0
1
0
1
0
1
Selection of CPU/Peripheral
Hardware Clock (fCLK)
fIH
fIH/2
fIH/2²
fIH/2³
fIH/2^{4 Note}
fIH/2^{5 Note}
Note Setting is prohibited when fIH = 1 MHz.
Caution If switching the CPU/peripheral hardware clock from the high-speed system clock to the
internal high-speed oscillation clock after restarting the internal high-speed oscillation
clock, do so after 10 μs or more have elapsed.
If the switching is made immediately after the internal high-speed oscillation clock is
restarted, the accuracy of the internal high-speed oscillation cannot be guaranteed for 10 μs.
(3) Example of setting procedure when stopping the internal high-speed oscillation clock
The internal high-speed oscillation clock can be stopped in the following two ways.
• Executing the STOP instruction
• Setting HIOSTOP to 1
(a) To execute a STOP instruction
<1> Setting of peripheral hardware
Stop peripheral hardware that cannot be used in the STOP mode (for peripheral hardware that cannot be
used in STOP mode, see CHAPTER 21 STANDBY FUNCTION).
<2> Setting the X1 clock oscillation stabilization time after STOP mode is released
If the X1 clock oscillates before the STOP mode is entered, set the value of the OSTS register before
executing the STOP instruction.
<3> Executing the STOP instruction
When the STOP instruction is executed, the system is placed in the STOP mode and internal high-speed
oscillation clock is stopped.
R01UH0004EJ0501 Rev.5.01
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Jun 20, 2011