UPD78F1502AGK-GAK-AX Datasheet, PDF (320/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 6 TIMER ARRAY UNIT
Figure 6-40. Operation Procedure of Interval Timer/Square Wave Output Function (1/2)
Software Operation
Hardware Status
TAU
default
setting
Power-off status
(Clock supply is stopped and writing to each register is
disabled.)
Sets the TAU0EN or TAU1EN bits of the PER0
register to 1.
Power-on status. Each channel stops operating.
(Clock supply is started and writing to each register is
enabled.)
Sets the TPSm register.
Determines clock frequencies of CKm0 and CKm1.
Channel
default
setting
Sets the TMRmn register (determines operation mode of
channel).
If timer input is selected for the count clock, set the timer
input (TIpq pin input, fSUB/4, fSUB/2, or INTRTCI) by using
the TISpq, SDIV, and RTCISpq bits.
Sets interval (period) value to the TDRmn register.
Channel stops operating.
(Clock is supplied and some power is consumed.)
To use the TOpq output
Clears the TOMpq bit of the TOMm register to 0
(toggle mode).
Clears the TOLpq bit to 0.
Sets the TOpq bit and determines default level of the
TOpq output.
Sets TOEpq to 1 and enables operation of TOpq.
Clears the port register and port mode register to 0.
The TOmn pin goes into Hi-Z output state.
The TOpq default setting level is output when the port mode
register is in the output mode and the port register is 0.
TOpq does not change because channel stops operating.
The TOpq pin outputs the TOpq set level.
Operation
start
Sets TOEpq to 1 (only when operation is resumed).
Sets the TSmn bit to 1.
The TSmn bit automatically returns to 0 because it is a
trigger bit.
TEmn = 1, and count operation starts.
Value of TDRmn is loaded to TCRmn at the count clock
input. INTTMmn is generated and TOpq performs toggle
operation if the MDmn0 bit of the TMRmn register is 1.
During
operation
Set values of TMRmn, TOMp, and TOLp registers cannot
be changed.
Set value of the TDRmn register can be changed.
The TCRmn register can always be read.
The TSRmn register is not used.
Set values of the TOp and TOEp registers can be
changed.
Counter (TCRmn) counts down. When count value reaches
0000H, the value of TDRmn is loaded to TCRmn again and
the count operation is continued. By detecting TCRmn =
0000H, INTTMmn is generated and TOmn performs toggle
operation.
After that, the above operation is repeated.
Operation The TTmn bit is set to 1.
stop
The TTmn bit automatically returns to 0 because it is a
trigger bit.
TEmn = 0, and count operation stops.
TCRmn holds count value and stops.
The TOpq output is not initialized but holds current status.
TOEpq is cleared to 0 and value is set to TOp register. The TOpq pin outputs the TOpq set level.
Remark
mn: Unit number + Channel number, pq: Unit number + Channel number (only for channels provided with
timer I/O pins)
78K0R/LF3: m = 0, 1, mn = 00 to 07, 10 to 13, pq = 00 to 04, 07
78K0R/LG3: m = 0, 1, mn = 00 to 07, 10 to 13, pq = 00 to 07
78K0R/LH3: m = 0, 1, mn = 00 to 07, 10 to 13, pq = 00 to 07, 10 to 13
R01UH0004EJ0501 Rev.5.01
304
Jun 20, 2011