UPD78F1502AGK-GAK-AX Datasheet, PDF (744/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 18 DMA CONTROLLER
Figure 18-8. Example of Setting of Consecutively Capturing A/D Conversion Results
Start
DEN0 = 1
DEN1 = 1
DSA0 = 10H
DRA0 = F100H
DBC0 = 0100H
DMC0 = 06H
DSA1 = 10H
DRA1 = F101H
DBC1 = 00FFH
DMC1 = 46H
Setting for CSI transfer
DST0 = 1
DST1 = 1
Write dummy data to
SIO00 (= SDR00 [7:0])
INTCSI00 occurs.
User program
processing
INTDMA0 occurs.
DST0 = 0 ^Note
DEN0 = 0
RETI
INTDMA1 occurs.
DST1 = 0 ^Note
DMA0 transfer CSI reception
DMA1 transfer Writing dummy data
DEN1 = 0
RETI
Hardware operation
End
Note
The DSTn flag is automatically cleared to 0 when a DMA transfer is completed.
Writing the DENn flag is enabled only when DSTn = 0. To terminate a DMA transfer without waiting for
occurrence of the interrupt of DMAn (INTDMAn), set DSTn to 0 and then DENn to 0 (for details, refer to 18.5.7
Forcible termination by software).
Because no CSI interrupt is generated when reception starts during CSI master reception, dummy data is written using
software in this example.
The received data is automatically transferred from the first byte (In successive reception mode, the data that is to be
received when the first buffer empty interrupt occurs is invalid because the valid data has not been received.).
A DMA interrupt (INTDMA1) occurs when the last dummy data has been writing to the data register. A DMA interrupt
(INTDMA0) occurs when the last received data has been read from the data register. To restart the DMA transfer, the CSI
transfer must be completed.
R01UH0004EJ0501 Rev.5.01
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Jun 20, 2011