UPD78F1502AGK-GAK-AX Datasheet, PDF (920/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 31 ELECTRICAL SPECIFICATIONS
(2) Serial interface: Serial array unit (3/18)
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD ≤ 5.5 V, VSS = EVSS = AVss = 0 V)
(c) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input)
Parameter
SCKp cycle time
SCKp high-/low-level width
SIp setup time
(to SCKp↑) ^{Note 1}
SIp hold time
(from SCKp↑) ^{Note 2}
Delay time from SCKp↓ to
SOp output ^{Note 3}
Symbol
Conditions
tKCY2
4.0 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD <
4.0 V
16 MHz < fMCK
fMCK ≤ 16 MHz
1.8 V ≤ VDD <
2.7 V
16 MHz < fMCK
fMCK ≤ 16 MHz
tKH2,
tKL2
tSIK2
MIN.
6/fMCK
8/fMCK
6/fMCK
8/fMCK
6/fMCK
tKCY2/2
TYP.
MAX.
80
Unit
ns
ns
ns
ns
ns
ns
ns
tKSI2
1/fMCK+50
ns
tKSO2
C = 30
pF^{Note 4}
4.0 V ≤ VDD = EVDD ≤ 5.5 V
2.7 V ≤ VDD = EVDD < 4.0 V
1.8 V ≤ VDD = EVDD < 2.7 V
2/fMCK+45
ns
2/fMCK+57
ns
2/fMCK+125
ns
Notes 1.
2.
3.
4.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓”
when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes
“from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
C is the load capacitance of the SCKp and SOp output lines.
Caution Select the normal input buffer for SIp and SCKp and the normal output mode for SOp by using the PIMg
and POMx registers.
Remarks 1.
2.
p: CSI number (p = 00, 01, 10, 20), g: PIM number (g = 1, 7), x: POM number (x = 1, 7, 8)
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of the SMRmn register. m: Unit number (m = 0, 1),
n: Channel number (n = 0 to 2))
R01UH0004EJ0501 Rev.5.01
904
Jun 20, 2011