UPD78F1502AGK-GAK-AX Datasheet, PDF (1005/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
Function
Details of
Function
APPENDIX C LIST OF CAUTIONS
Cautions
(33/39)
Page
Low-
voltage
detector
Used as reset Be sure to execute <1>. When LVIMK = 0, an interrupt may occur immediately after p.811 _†
(when detecting the processing in <4>.
level of supply
voltage (VDD))
If supply voltage (VDD) ≥ detection voltage (VLVI) when LVIMD is set to 1, an internal p.811 _†
reset signal is not generated.
(LVIOFF = 1)
Used as reset Even when the LVI default start function is used, if it is set to LVI operation p.812 _†
(when detecting prohibition by the software, it operates as follows:
level of supply • Does not perform low-voltage detection during LVION = 0.
voltage (VDD)) • If a reset is generated while LVION = 0, LVION will be re-set to 1 when the CPU
(LVIOFF = 0)
starts after reset release. There is a period when low-voltage detection cannot be
performed normally, however, when a reset occurs due to WDT and illegal
instruction execution.
This is due to the fact that while the pulse width detected by LVI must be 200 μs
max., LVION = 1 is set upon reset occurrence, and the CPU starts operating
without waiting for the LVI stabilization time.
Used as reset Be sure to execute <1>. When LVIMK = 0, an interrupt may occur immediately after p.813 _†
(when detecting the processing in <3>.
level of input
If input voltage from external input pin (EXLVI) ≥ detection voltage (VEXLVI = 1.21 V p.813 _†
voltage from
(TYP.)) when LVIMD is set to 1, an internal reset signal is not generated.
external input _{Input voltage from external input pin (EXLVI) must be EXLVI < VDD.}
p.813 _†
pin (EXLVI))
Used as
Even when the LVI default start function is used, if it is set to LVI operation p.819 _†
interrupt (when prohibition by the software, it operates as follows:
detecting level of • Does not perform low-voltage detection during LVION = 0.
supply voltage • If a reset is generated while LVION = 0, LVION will be re-set to 1 when the CPU
(VDD)) (LVIOFF = starts after reset release. There is a period when low-voltage detection cannot be
0)
performed normally, however, when a reset occurs due to WDT and illegal
instruction execution.
This is due to the fact that while the pulse width detected by LVI must be 200 μs
max., LVION = 1 is set upon reset occurrence, and the CPU starts operating
without waiting for the LVI stabilization time.
When the LVI default start function (bit 0 (LVIOFF) of 000C1H = 0) is used, the p.819 _†
LVIRF flag may become 1 from the beginning due to the power-on waveform.
For details of RESF, see CHAPTER 22 RESET FUNCTION.
Used as
Input voltage from the external input pin (EXLVI) must be EXLVI < VDD.
p.821 _†
interrupt (when
detecting level of
input voltage
from external
input pin
(EXLVI))
R01UH0004EJ0501 Rev.5.01
989
Jun 20, 2011