UPD78F1502AGK-GAK-AX Datasheet, PDF (990/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
Function
Details of
Function
APPENDIX C LIST OF CAUTIONS
Cautions
(18/39)
Page
A/D
converter
Operating
Shift to STOP mode after stopping the A/D converter (by setting bit 7 (ADCS) of the p.414 _†
current in STOP A/D converter mode register (ADM) to 0). The operating current can be reduced by
mode
setting bit 0 (ADCE) of the A/D converter mode register (ADM) to 0 at the same time.
When using normal mode 2 (LV1 = 0, LV0 = 1) or low voltage mode (LV1 = 1, LV0 =
0), clear bit 1 (VRGV) and bit 0 (VRON) of the analog reference voltage control
register (ADVRC) to 0, and then shift to STOP mode.
To restart from the standby status, clear bit 0 (ADIF) of interrupt request flag register
1L (IF1L) to 0 and start operation.
Input range of Observe the rated range of the ANI0 to ANI10, ANI15 input voltage. If a voltage of p.414 _†
ANI0 to ANI10, AVDD0 or higher and AVSS or lower (even in the range of absolute maximum ratings)
ANI15
is input to an analog input channel, the converted value of that channel becomes
undefined. In addition, the converted values of the other channels may also be
affected.
Conflicting
Conflict between A/D conversion result register (ADCR, ADCRH) write and ADCR or p.414 _†
operations
ADCRH read by instruction upon the end of conversion
ADCR or ADCRH read has priority. After the read operation, the new conversion
result is written to ADCR or ADCRH.
Conflict between ADCR or ADCRH write and A/D converter mode register (ADM) p.414 _†
write, analog input channel specification register (ADS), or A/D port configuration
register (ADPC) write upon the end of conversion
ADM, ADS, or ADPC write has priority. ADCR or ADCRH write is not performed, nor
is the conversion end interrupt signal (INTAD) generated.
Noise
To maintain the 12-bit resolution, attention must be paid to noise input to the AVREFP p.414 _†
countermeasures pin and pins ANI0 to ANI10, ANI15.
<1> Connect a capacitor with a low equivalent resistance and a good frequency
response to the power supply.
<2> The higher the output impedance of the analog input source, the greater the
influence. To reduce the noise, connecting external C as shown in Figure 10-28
is recommended.
<3> Do not switch these pins with other pins during conversion.
<4> The accuracy is improved if the HALT mode is set immediately after the start of
conversion.
ANI0 to ANI10, The analog input pins (ANI0 to ANI7) are also used as input port pins (P20 to P27). p.415 _†
ANI15
The analog input pins (ANI8 to ANI10, ANI15) are also used as input port pins (P150
to P152, P157).
When A/D conversion is performed with any of ANI0 to ANI10, and ANI15 selected,
do not access P20 to P27, P150 to P152, and P157 while conversion is in progress;
otherwise the conversion resolution may be degraded. It is recommended to select
pins used as P20 to P27, P150 to P152, and P157 starting with the ANI0/P20 that is
the furthest from AVDD0.
If the pins adjacent to the pins currently used for A/D conversion are used as digital p.415 _†
I/O port, the expected value of the A/D conversion may not be obtained due to
coupling noise. Therefore, make sure that digital pulses are not input to or output
from the pins adjacent to the pin undergoing A/D conversion.
If any pin among pins of ports 2 and 15 is used as digital output port during A/D p.415 _†
conversion, the expected value of the A/D conversion may not be obtained due to
coupling noise. Therefore, make sure that digital pulses are not output to pins of
ports 2 and 15 during A/D conversion.
R01UH0004EJ0501 Rev.5.01
974
Jun 20, 2011