UPD78F1502AGK-GAK-AX Datasheet, PDF (621/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 15 SERIAL INTERFACE IICA
15.5.8 Interrupt request (INTIICA) generation timing and wait control
The setting of bit 3 (WTIM) of IICA control register 0 (IICCTL0) determines the timing by which INTIICA is generated
and the corresponding wait control, as shown in Table 15-2.
WTIM
0
1
Table 15-2. INTIICA Generation Timing and Wait Control
During Slave Device Operation
Address
Data Reception Data Transmission
9^{Notes 1, 2}
9^{Notes 1, 2}
8^{Note 2}
9^{Note 2}
8^{Note 2}
9^{Note 2}
During Master Device Operation
Address
Data Reception Data Transmission
9
8
8
9
9
9
Notes 1. The slave device’s INTIICA signal and wait period occurs at the falling edge of the ninth clock only when
there is a match with the address set to the slave address register (SVA).
At this point, ACK is generated regardless of the value set to IICCTL0’s bit 2 (ACKE). For a slave device that
has received an extension code, INTIICA occurs at the falling edge of the eighth clock.
However, if the address does not match after restart, INTIICA is generated at the falling edge of the 9th
clock, but wait does not occur.
2. If the received address does not match the contents of the slave address register (SVA) and extension code
is not received, neither INTIICA nor a wait occurs.
Remark The numbers in the table indicate the number of the serial clock’s clock signals. Interrupt requests and wait
control are both synchronized with the falling edge of these clock signals.
(1) During address transmission/reception
• Slave device operation: Interrupt and wait timing are determined depending on the conditions described in
Notes 1 and 2 above, regardless of the WTIM bit.
• Master device operation: Interrupt and wait timing occur at the falling edge of the ninth clock regardless of the
WTIM bit.
(2) During data reception
• Master/slave device operation: Interrupt and wait timing are determined according to the WTIM bit.
(3) During data transmission
• Master/slave device operation: Interrupt and wait timing are determined according to the WTIM bit.
(4) Wait cancellation method
The four wait cancellation methods are as follows.
• Writing data to IICA shift register (IICA)
• Setting bit 5 (WREL) of IICA control register 0 (IICCTL0) (canceling wait)
• Setting bit 1 (STT) of IICCTL0 register (generating start condition)^Note
• Setting bit 0 (SPT) of IICCTL0 register (generating stop condition)^Note
Note Master only.
When an 8-clock wait has been selected (WTIM = 0), the presence/absence of ACK generation must be
determined prior to wait cancellation.
(5) Stop condition detection
INTIICA is generated when a stop condition is detected (only when SPIE = 1).
R01UH0004EJ0501 Rev.5.01
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Jun 20, 2011