UPD78F1502AGK-GAK-AX Datasheet, PDF (597/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 15 SERIAL INTERFACE IICA
15.2 Configuration of Serial Interface IICA
Serial interface IICA includes the following hardware.
Table 15-1. Configuration of Serial Interface IICA
Item
Registers
Control registers
Configuration
IICA shift register (IICA)
Slave address register (SVA)
Peripheral enable register 0 (PER0)
IICA control register 0 (IICCTL0)
IICA status register (IICS)
IICA flag register (IICF)
IICA control register 1 (IICCTL1)
IICA low-level width setting register (IICWL)
IICA high-level width setting register (IICWH)
Port mode register 6 (PM6)
Port register 6 (P6)
(1) IICA shift register (IICA)
IICA is used to convert 8-bit serial data to 8-bit parallel data and vice versa in synchronization with the serial clock.
IICA can be used for both transmission and reception.
The actual transmit and receive operations can be controlled by writing and reading operations to IICA.
Cancel the wait state and start data transfer by writing data to IICA during the wait period.
IICA can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears IICA to 00H.
Figure 15-3. Format of IICA Shift Register (IICA)
Address: FFF50H After reset: 00H R/W
Symbol
7
6
5
4
3
2
1
0
IICA
Cautions 1. Do not write data to IICA during data transfer.
2. Write or read IICA only during the wait period. Accessing IICA in a communication state other
than during the wait period is prohibited. When the device serves as the master, however,
IICA can be written only once after the communication trigger bit (STT) is set to 1.
3. When communication is reserved, write data to IICA after the interrupt triggered by a stop
condition is detected.
(2) Slave address register (SVA)
This register stores seven bits of local addresses {A6, A5, A4, A3, A2, A1, A0} when in slave mode.
SVA can be set by an 8-bit memory manipulation instruction.
However, rewriting to this register is prohibited while STD = 1 (while the start condition is detected).
Reset signal generation clears SVA to 00H.
R01UH0004EJ0501 Rev.5.01
581
Jun 20, 2011