UPD78F1502AGK-GAK-AX Datasheet, PDF (249/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 5 CLOCK GENERATOR
(2) Example of setting procedure when using the external main system clock
<1> Setting P121/X1 and P122/X2/EXCLK pins (CMC register)
EXCLK
1
OSCSEL
1
0
OSCSELS
0
0
0/1
0
AMPHS1 AMPHS0
0/1
0/1
AMPH
0/1
Remark For setting of the P123/XT1 and P124/XT2 pins, see 5.6.3 (1) Example of setting procedure
when oscillating the subsystem clock.
<2> Controlling external main system clock input (CSC register)
When MSTOP is cleared to 0, the input of the external main system clock is enabled.
Cautions 1. The CMC register can be written only once after reset release, by an 8-bit memory
manipulation instruction.
Therefore, it is necessary to also set the value of the OSCSELS bits at the same time. For
OSCSELS bits, see 5.6.3 Example of controlling subsystem clock.
2. Set the external main system clock after the supply voltage has reached the operable voltage
of the clock to be used (see CHAPTER 31 ELECTRICAL SPECIFICATIONS).
(3) Example of setting procedure when using high-speed system clock as CPU/peripheral hardware clock
<1> Setting high-speed system clock oscillation^Note
(See 5.6.1 (1) Example of setting procedure when oscillating the X1 clock and (2) Example of setting
procedure when using the external main system clock.)
Note The setting of <1> is not necessary when high-speed system clock is already operating.
<2> Setting the high-speed system clock as the source clock of the CPU/peripheral hardware clock and setting
the division ratio of the set clock (CKC register)
MCM0
1
MDIV2
0
0
0
0
1
1
MDIV1
0
0
1
1
0
0
MDIV0
0
1
0
1
0
1
Selection of CPU/Peripheral
Hardware Clock (fCLK)
fMX
fMX/2
fMX/2²
fMX/2³
fMX/2⁴
fMX/2^{5 Note}
Note Setting is prohibited when fMX < 4 MHz.
R01UH0004EJ0501 Rev.5.01
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Jun 20, 2011