UPD78F1502AGK-GAK-AX Datasheet, PDF (809/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 22 RESET FUNCTION
Table 22-2. Hardware Statuses After Reset Acknowledgment (1/4)
Program counter (PC)
Hardware
Stack pointer (SP)
Program status word (PSW)
RAM
Data memory
General-purpose registers
Port registers (P0 to P15) (output latches)
Port mode registers (PM0 to PM12, PM14, PM15)
Port input mode registers 1, 7 (PIM1, PIM7)
Port output mode registers 1, 7, 8 (POM1, POM7, POM8)
Pull-up resistor option registers (PU0, PU1, PU3 to PU5, PU7 to PU10, PU12, PU14)
Clock operation mode control register (CMC)
Clock operation status control register (CSC)
Processor mode control register (PMC)
System clock control register (CKC)
20 MHz internal high-speed oscillation control register (DSCCTL)
Oscillation stabilization time counter status register (OSTC)
Oscillation stabilization time select register (OSTS)
Noise filter enable registers 0, 1 (NFEN0, NFEN1)
Peripheral enable registers 0 (PER0)
Operation speed mode control register (OSMC)
Input switch control register (ISC)
Timer array units
0, 1 (TAU0, TAU1)
Timer data registers 00, 01, 02, 03, 04, 05, 06, 07, 10, 11, 12, 13 (TDR00,
TDR01, TDR02, TDR03, TDR04, TDR05, TDR06, TDR07, TDR10, TDR11,
TDR12, TDR13)
Timer mode registers 00, 01, 02, 03, 04, 05, 06, 07, 10, 11, 12, 13 (TMR00,
TMR01, TMR02, TMR03, TMR04, TMR05, TMR06, TMR07, TMR10, TMR11,
TMR12, TMR13)
Timer status registers 00, 01, 02, 03, 04, 05, 06, 07, 10, 11, 12, 13 (TSR00,
TSR01, TSR02, TSR03, TSR04, TSR05, TSR06, TSR07, TSR10, TSR11,
TSR12, TSR13)
Timer input select register 0, 1 (TIS0, TIS1)
Timer channel counter registers 00, 01, 02, 03, 04, 05, 06, 07, 10, 11, 12, 13
(TCR00, TCR01, TCR02, TCR03, TCR04, TCR05, TCR06, TCR07, TCR10,
TCR11, TCR12, TCR13)
Timer channel enable status registers 0, 1 (TE0, TE1)
Timer channel start trigger registers 0, 1 (TS0, TS1)
After Reset
Acknowledgment^{Note 1}
The contents of the
reset vector table
(0000H, 0001H) are set.
Undefined
06H
Undefined^{Note 2}
Undefined^{Note 2}
00H
FFH
00H
00H
00H
00H
C0H
00H
09H
00H
00H
07H
00H
00H
00H
00H
0000H
0000H
0000H
00H
FFFFH
0000H
0000H
Notes 1.
2.
During reset signal generation or oscillation stabilization time wait, only the PC contents among the hardware
statuses become undefined. All other hardware statuses remain unchanged after reset.
When a reset is executed in the standby mode, the pre-reset status is held even after reset.
Remark The SFR and 2nd SFR provided differ depending on the product. Refer to 3.2.4 Special function registers
(SFRs) and 3.2.5 Extended special function registers (2nd SFRs: 2nd Special Function Registers).
R01UH0004EJ0501 Rev.5.01
793
Jun 20, 2011