UPD78F1502AGK-GAK-AX Datasheet, PDF (666/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 15 SERIAL INTERFACE IICA
The meanings of <3> to <10> in (2) Address ~ data ~ data in Figure 15-32 are explained below.
<3> If the address received matches the address of a slave device^Note, that slave device sends an ACK by
hardware to the master device. The ACK is detected by the master device (ACKD = 1) at the rising edge of
the 9th clock.
<4> The master device issues an interrupt (INTIICA: end of address transmission) at the falling edge of the 9th
clock, and the slave device whose address matched the transmitted slave address also issues an interrupt
(INTIICA: address match). The master device and slave device also set a wait status (SCL0 = 0)^Note when
the addresses match.
<5> The master device writes the data to transmit to the IICA shift register (IICA) and releases the wait status
that it set by the master device.
<6> If the slave device releases the wait status (WREL = 1), the master device starts transferring data to the
slave device.
<7> When data transfer is complete, the slave device sends an ACK by hardware to the master device. The
ACK is detected by the master device (ACKD = 1) at the rising edge of the 9th clock.
<8> The master device and slave device set a wait status (SCL0 = 0) at the falling edge of the 9th clock, and
both the master device and slave device issue an interrupt (INTIICA: end of transfer).
<9> The master device writes the data to transmit to the IICA register and releases the wait status that it set by
the master device.
<10> The slave device reads the received data and releases the wait status (WREL = 1). The master device then
starts transferring data to the slave device.
Note If the transmitted address does not match the address of the slave device, the slave device does not return
an ACK to the master device (NACK: SDA0 = 1). The slave device also does not issue the INTIICA interrupt
(address match) and does not set a wait status. The master device, however, issues the INTIICA interrupt
(end of address transmission) regardless of whether it receives an ACK or NACK.
Remark <1> to <15> in Figure 15-32 represent the entire procedure for communicating data using the I²C bus.
Figure 15-32 (1) Start condition ~ address ~ data shows the processing from <1> to <6>, Figure 15-32
(2) Address ~ data ~ data shows the processing from <3> to <10>, and Figure 15-32 (3) Data ~ data ~
stop condition shows the processing from <7> to <15>.
R01UH0004EJ0501 Rev.5.01
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Jun 20, 2011