UPD78F1502AGK-GAK-AX Datasheet, PDF (840/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 24 LOW-VOLTAGE DETECTOR
Figure 24-11. Example of Software Processing After Reset Release (1/2)
• If supply voltage fluctuation is 50 ms or less in vicinity of LVI detection voltage
Reset
Initialization
processing <1>
LVI reset
Setting LVI
; Check the reset source, etc.^Note
; Setting of detection level by LVIS.
The low-voltage detector operates (LVION = 1).
Setting timer array unit
(to measure 50 ms)
; fCLK = Internal high-speed oscillation clock (4.08 MHz (MAX.)) (default)
Source: fCLK (4.08 MHz (MAX.))/2¹¹,
where comparison value = 100: ≅ 50 ms
Timer starts (TS0n = 1).
Clearing WDT
Detection
Yes
voltage or higher
(LVIF = 0?)
No
Restarting timer array unit
(TT0n = 1 → TS0n = 1)
; The timer counter is cleared and the timer is started.
No
50 ms has passed?
(TMIF0n = 1?)
Yes
Initialization
processing <2>
; Initial setting for port.
Setting of division ratio of system clock,
such as setting of timer or A/D converter.
Note A flowchart is shown on the next page.
Remarks 1.
2.
If bit 2 (LVISEL) of the low voltage detection register (LVIM) is set to “1”, the meanings of the above
words change as follows.
• Supply voltage (VDD) → Input voltage from external input pin (EXLVI)
• Detection voltage (VLVI) → Detection voltage (VEXLVI = 1.21 V)
n = 0 to 7
R01UH0004EJ0501 Rev.5.01
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Jun 20, 2011