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UPD78F1502AGK-GAK-AX Datasheet, PDF (298/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers
78K0R/Lx3
CHAPTER 6 TIMER ARRAY UNIT
(12) Timer output mode register p (TOMp)
TOMp is used to control the timer output mode of each channel.
When a channel is used for the combination operation function (PWM output, one-shot pulse output, or multiple
PWM output), set the corresponding bit of the slave channel to 1.
The setting of each channel q by this register is reflected at the timing when the timer output signal is set or reset
while the timer output is enabled (TOEpq = 1).
TOMp can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of TOMp can be set with an 8-bit memory manipulation instruction with TOMpL.
Reset signal generation clears this register to 0000H.
Figure 6-21. Format of Timer Output Mode Register p (TOMp)
• 78K0R/LF3
Address: F01BEH, F01BFH After reset: 0000H R/W
Symbol
15 14 13 12 11 10 9
TOM0
0
0
0
0
0
0
0
8
7
6
0 TOM 0
07
5
4
3
2
1
0
0 TOM TOM TOM TOM TOM
04 03 02 01 00
• 78K0R/LG3
Address: F01BEH, F01BFH After reset: 0000H R/W
Symbol
15 14 13 12 11 10 9
TOM0
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0 TOM TOM TOM TOM TOM TOM TOM TOM
07 06 05 04 03 02 01 00
• 78K0R/LH3
Address: F01BEH, F01BFH After reset: 0000H R/W
Symbol
15 14 13 12 11 10 9
TOM0
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0 TOM TOM TOM TOM TOM TOM TOM TOM
07 06 05 04 03 02 01 00
Address: F01E6H, F01E7H After reset: 0000H R/W
Symbol
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
TOM1
0
0
0
0
0
0
0
0
0
0
0
0 TOM TOM TOM TOM
13 12 11 10
TOM
pq
Control of timer output mode of channel q
0 Toggle mode (to produce toggle output by timer interrupt request signal (INTTMpq))
1 Combination operation mode (set by the timer interrupt request signal (INITTMpq) of the master channel,
and reset by the timer interrupt request signal (INITTMpr) of the slave channel)
Cautions 1. For 78K0R/LF3, be sure to clear bits 15 to 8, 6 and 5 of TOM0 to “0”.
2. For 78K0R/LG3, be sure to clear bits 15 to 8 of TOM0 to “0”.
3. For 78K0R/LH3, be sure to clear bit 15 to 8 of TOM0, bits 15 to 4 of TOM1 to “0”.
(Remark is listed on the next page.)
R01UH0004EJ0501 Rev.5.01
282
Jun 20, 2011