UPD78F1502AGK-GAK-AX Datasheet, PDF (471/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 14 SERIAL ARRAY UNIT
(6) Serial status register mn (SSRmn)
SSRmn is a register that indicates the communication status and error occurrence status of channel n. The errors
indicated by this register are a framing error, parity error, and overrun error.
SSRmn can be read by a 16-bit memory manipulation instruction.
The lower 8 bits of SSRmn can be set with an 8-bit memory manipulation instruction with SSRmnL.
Reset signal generation clears this register to 0000H.
Figure 14-9. Format of Serial Status Register mn (SSRmn) (1/2)
Address: F0100H, F0101H (SSR00) to F0106H, F0107H (SSR03), After reset: 0000H R
F0140H, F0141H (SSR10), F0142H, F0143H (SSR11),
F0144H, F0145H (SSR12), F0146H, F0147H (SSR13)
Symbol
15 14 13 12 11 10 9
8
7
6
5
4
SSRmn
0
0
0
0
0
0
0
0
0 TSF BFF 0
mn mn
3
2
1
0
0 FEF PEF OVF
mn mn mn
Note
Note
Note
TSF
Communication status indication flag of channel n
mn
0 Communication is not under execution.
1 Communication is under execution.
Because this flag is an updating flag, it is automatically cleared when the communication operation is completed.
This flag is cleared also when the STmn/SSmn bit is set to 1.
BFF
Buffer register status indication flag of channel n
mn
0 Valid data is not stored in the SDRmn register.
1 Valid data is stored in the SDRmn register.
This is an updating flag. It is automatically cleared when transfer from the SDRmn register to the shift register is
completed. During reception, it is automatically cleared when data has been read from the SDRmn register. This
flag is cleared also when the STmn/SSmn bit is set to 1.
This flag is automatically set if transmit data is written to the SDRmn register when the TXEmn bit of the SCRmn
register = 1 (transmission or reception mode in each communication mode). It is automatically set if receive data is
stored in the SDRmn register when the RXEmn bit of the SCRmn register = 1 (transmission or reception mode in
each communication mode). It is also set in case of a reception error.
If data is written to the SDRmn register when BFFmn = 1, the transmit/receive data stored in the register is
discarded and an overrun error (OVFmn = 1) is detected.
Note Only SSR12 register does not have FET12, PET12, and OVF12.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
R01UH0004EJ0501 Rev.5.01
455
Jun 20, 2011