UPD78F1502AGK-GAK-AX Datasheet, PDF (300/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 6 TIMER ARRAY UNIT
(14) Noise filter enable registers 1, 2 (NFEN1, NFEN2)
NFEN1 and NFEN2 are used to set whether the noise filter can be used for the timer input signal to each
channel.
Enable the noise filter by setting the corresponding bits to 1 on the pins in need of noise removal.
When the noise filter is ON, match detection and synchronization of the 2 clocks is performed with the
CPU/peripheral hardware clock (fCLK). When the noise filter is OFF, only synchronization is performed with the
CPU/peripheral hardware clock (fCLK).
NFEN1, NFEN2 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
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Jun 20, 2011