UPD78F1502AGK-GAK-AX Datasheet, PDF (673/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 15 SERIAL INTERFACE IICA
Figure 15-33. Example of Slave to Master Communication
(When 8-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (2/3)
(2) Address ~ data ~ data
Master side
IICA
ACKD
(ACK detection)
WTIM
(8 or 9 clock wait)
ACKE
(ACK control) ^H
MSTS
(communication status) ^H
STT
(ST trigger)
L
SPT
(SP trigger)
L
WREL
(wait cancellation)
INTIICA
(interrupt)
TRC
(transmit/receive)
L
<5>
Note 1
<7>
Note 1
<9>
Bus line
SCL0 (bus)
(clock line)
<4>
SDA0 (bus)
(data line)
R ^ACK
D17
<3>
Slave side
IICA
ACKD
(ACK detection)
STD
(ST detection)
SPD
(SP detection) ^L
<6> ^{Note 2}
WTIM
(8 or 9 clock wait)
H
ACKE
(ACK control) ^H
MSTS
(communication status) ^L
WREL
(wait cancellation) ^L
INTIICA
(interrupt)
TRC
(transmit/receive) ^H
<8>
<11>
D16 D15 D14 D13 D12 D11 D10
ACK
D27
<10>
<12> Note 2
: Wait state by master device
: Wait state by slave device
: Wait state by master and slave devices
Notes 1. To cancel master wait, write “FFH” to IICA or set the WREL bit.
2. Write data to IICA, not setting the WREL bit, in order to cancel a wait state during slave transmission.
R01UH0004EJ0501 Rev.5.01
657
Jun 20, 2011