UPD78F1502AGK-GAK-AX Datasheet, PDF (459/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 14 SERIAL ARRAY UNIT
Figure 14-2 shows the block diagram of serial array unit 1.
Figure 14-2. Block Diagram of Serial Array Unit 1
Serial output register 1 (SO1)
0
0
0
0
1
1
1 CKO10 0
0
0
Peripheral enable
register 0 (PER0)
SAU1EN
PRS
113
Serial clock select register 1 (SPS1)
PRS PRS PRS PRS PRS PRS
112 111 110 103 102 101
PRS
100
4
4
fCLK
INTTM03
Prescaler
fCLK/2⁰ to fCLK/2¹¹
fCLK/2⁰ to
fCLK/2¹¹
Noise filter enable
register 0 (NFEN0)
0
1 SO12 1 SO10
SNFEN SNFEN
30
20
Serial channel enable
SE13 SE12 SE11 SE10 status register 1 (SE1)
Serial channel start
SS13 SS12 SS11 SS10 _{register 1 (SS1)}
Serial channel stop
ST13 ST12 ST11 ST10 register 1 (ST1)
Serial output enable
0 SOE12 0 SOE10 _{register 1 (SOE1)}
Serial output level
0 SOL12 0 SOL10 _{register 1 (SOL1)}
Selector
Selector
Serial clock I/O pin
(when CSI20: SCK20)
(when IIC20: SCL20)
Serial data input pin
(when CSI20: SI20)
(when IIC20: SDA20)
(when UART2: RxD2)
Channel 0
CK11
CK10
Serial data register 10 (SDR10)
(Clock division setting block) (Buffer register block)
Edge
SCK
detection
MCK
TCLK
Shift register
Output latch
(P11 or P12)
PM11 or PM12
Output
controller
PM10
Output latch
(P10)
Noise
elimination
enabled/
disabled
Edge/level
detection
SNFEN20
CKS10 CCS10 STS10 MD102 MD101
Serial mode register 10 (SMR10)
Communication controller
Interrupt
controller
Mode selection
CSI20 or IIC20
or UART2
(for transmission)
Serial flag clear trigger
register 10 (SIR10)
FECT PECT OVCT
10 10 10
Clear
Error controller
Error
information
TXE RXE DAP CKP EOC PTC PTC DIR SLC SLC DLS DLS DLS
10 10 10 10 10 101 100 10 101 100 102 101 100
Serial communication operation setting register 10 (SCR10)
TSF BFF FEF PEF OVF
10 10 10 10 10
Serial status register 10 (SSR10)
Serial data output pin
(when CSI20: SO20)
(when IIC20: SDA20)
(when UART2: TxD2)
Serial transfer end interrupt
(when CSI20: INTCSI20)
(when IIC20: INTIIC20)
(when UART2: INTST2)
When UART2
Channel 1
CK11
CK10
Edge/level
detection
Communication controller
Mode selection
UART2
(for reception)
Error controller
Serial transfer end interrupt
(when UART2: INTSR2)
Serial transfer error interrupt
(INTSRE2)
Serial data input pin
(when UART3: RxD3)
CK11
CK10
Channel 2 (LIN-bus supported)
Noise
elimination
enabled/
disabled
SNFEN30
CK11
CK10
Channel 3 (LIN-bus supported)
When UART3
Edge/level
detection
Communication controller
Mode selection
UART3
(for transmission)
Serial data output pin
(when UART3: TXD3)
Serial transfer end interrupt
(when UART3: INTST3)
Communication controller
Mode selection
UART3
(for reception)
Error controller
Serial transfer end interrupt
(when UART3: INTSR3)
Serial transfer error interrupt
(INTSRE3)
R01UH0004EJ0501 Rev.5.01
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Jun 20, 2011