UPD78F1502AGK-GAK-AX Datasheet, PDF (464/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 14 SERIAL ARRAY UNIT
Figure 14-5. Format of Serial Clock Select Register m (SPSm)
Address: F0126H, F0127H (SPS0), F0166H, F0167H (SPS1) After reset: 0000H R/W
Symbol
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
SPSm
0
0
0
0
0
0
0
0 PRS PRS PRS PRS PRS PRS PRS PRS
m13 m12 m11 m10 m03 m02 m01 m00
PRS PRS PRS PRS
mp3 mp2 mp1 mp0
Section of operation clock (CKmp) ^{Note 1}
fCLK = 2 MHz
fCLK = 5 MHz fCLK = 10 MHz
fCLK = 20 MHz
0
0
0
0 fCLK
2 MHz
5 MHz
10 MHz
20 MHz
0
0
0
1 fCLK/2
1 MHz
2.5 MHz
0
0
1
0
fCLK/2²
500 kHz
1.25 MHz
0
0
1
1
fCLK/2³
250 kHz
625 kHz
0
1
0
0
fCLK/2⁴
125 kHz
313 kHz
0
1
0
1
fCLK/2⁵
62.5 kHz
156 kHz
0
1
1
0
fCLK/2⁶
31.3 kHz
78.1 kHz
0
1
1
1
fCLK/2⁷
15.6 kHz
39.1 kHz
1
0
0
0
fCLK/2⁸
7.81 kHz
19.5 kHz
1
0
0
1
fCLK/2⁹
3.91 kHz
9.77 kHz
1
0
1
0
fCLK/2¹⁰
1.95 kHz
4.88 kHz
1
0
1
1
fCLK/2¹¹
977 Hz
2.44 kHz
1
1
1
1 INTTM02 if m = 0, INTTM03 if m = 1^{Note 2}
5 MHz
2.5 MHz
1.25 MHz
625 kHz
313 kHz
156 kHz
78.1 kHz
39.1 kHz
19.5 kHz
9.77 kHz
4.88 kHz
10 MHz
5 MHz
2.5 MHz
1.25 MHz
625 kHz
313 kHz
156 kHz
78.1 kHz
39.1 kHz
19.5 kHz
9.77 kHz
Other than above
Setting prohibited
Notes 1. When changing the clock selected for fCLK (by changing the system clock control register (CKC) value),
do so after having stopped (STm = 000FH) the operation of the serial array unit (SAUm). When selecting
INTTM02 and INTTM03 for the operation clock, also stop the timer array unit (TAU0) (TT0 = 00FFH).
2. SAUm can be operated at a fixed division ratio of the subsystem clock, regardless of the fCLK frequency
(main system clock, subsystem clock), by operating the interval timer for which fSUB/4 has been selected
as the count clock (setting TIS02 (if m = 0) or TIS03 (if m = 1) of the TIS0 register to 1) and selecting
INTTM02 and INTTM03 by using the SPSm register in channels 2 and 3 of TAU0. When changing fCLK,
however, SAUm and TAU0 must be stopped as described in Note 1 above.
Cautions 1. Be sure to clear bits 15 to 8 to “0”.
2. After setting the SAUmEN to 1, be sure to set the SPSm register after 4 or more clocks have
elapsed.
Remarks 1. fCLK: CPU/peripheral hardware clock frequency
fSUB: Subsystem clock frequency
2. m: Unit number (m = 0, 1), p = 0, 1
R01UH0004EJ0501 Rev.5.01
448
Jun 20, 2011