UPD78F1502AGK-GAK-AX Datasheet, PDF (833/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 24 LOW-VOLTAGE DETECTOR
24.4.2 When used as interrupt
(1) When detecting level of supply voltage (VDD)
(a) When LVI default start function stopped is set (LVIOFF = 1)
• When starting operation
<1> Mask the LVI interrupt (LVIMK = 1).
<2> Clear bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 0 (detects level of supply voltage
(VDD)) (default value).
Clear bit 1 (LVIMD) of LVIM to 0 (generates interrupt signal when the level is detected) (default value).
<3> Set the detection voltage using bits 3 to 0 (LVIS3 to LVIS0) of the low-voltage detection level selection
register (LVIS).
<4> Set bit 7 (LVION) of LVIM to 1 (enables LVI operation).
<5> Use software to wait for the following periods of time (Total 210 μs).
• Operation stabilization time (10 μs (MAX.))
• Minimum pulse width (200 μs (MIN.))
<6> Confirm that “supply voltage (VDD) ≥ detection voltage (VLVI)” when detecting the falling edge of VDD, or
“supply voltage (VDD) < detection voltage (VLVI)” when detecting the rising edge of VDD, at bit 0 (LVIF) of
LVIM.
<7> Clear the interrupt request flag of LVI (LVIIF) to 0.
<8> Release the interrupt mask flag of LVI (LVIMK).
<9> Execute the EI instruction (when vector interrupts are used).
Figure 24-8 shows the timing of the interrupt signal generated by the low-voltage detector. The numbers in this
timing chart correspond to <1> to <8> above.
• When stopping operation
Be sure to clear (0) LVION by using a 1-bit memory manipulation instruction.
R01UH0004EJ0501 Rev.5.01
817
Jun 20, 2011