UPD78F1502AGK-GAK-AX Datasheet, PDF (391/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 8 WATCHDOG TIMER
8.2 Configuration of Watchdog Timer
The watchdog timer includes the following hardware.
Item
Control register
Table 8-1. Configuration of Watchdog Timer
Configuration
Watchdog timer enable register (WDTE)
How the counter operation is controlled, overflow time, window open period, and interval interrupt are set by the option
byte.
Table 8-2. Setting of Option Bytes and Watchdog Timer
Setting of Watchdog Timer
Watchdog timer interval interrupt
Window open period
Controlling counter operation of watchdog timer
Overflow time of watchdog timer
Controlling counter operation of watchdog timer
(in HALT/STOP mode)
Option Byte (000C0H)
Bit 7 (WDTINT)
Bits 6 and 5 (WINDOW1, WINDOW0)
Bit 4 (WDTON)
Bits 3 to 1 (WDCS2 to WDCS0)
Bit 0 (WDSTBYON)
Remark For the option byte, see CHAPTER 26 OPTION BYTE.
Figure 8-1. Block Diagram of Watchdog Timer
WDTINT of option
byte (000C0H)
WDCS2 to WDCS0 of
option byte (000C0H)
Interval time controller
(Count value overflow time × 3/4)
Interval time interrupt
fIL
Clock
input
20-bit
fIL/2⁷ to fIL/2¹⁷
Overflow signal
Selector
counter
controller
WINDOW1 and
WINDOW0 of option
byte (000C0H)
Count clear
signal
Window size check
Window size
decision signal
Reset
output
controller
Internal reset signal
WDTON of option
byte (000C0H)
Watchdog timer enable
register (WDTE)
Write detector to
WDTE except ACH
Internal bus
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Jun 20, 2011