UPD78F1502AGK-GAK-AX Datasheet, PDF (728/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 17 MULTIPLIER/DIVIDER
(3) Multiplication/division data register C (MDCL, MDCH)
The MDCH and MDCL registers store remainder value of the operation result in the division mode. They are not
used in the multiplication mode.
MDCH and MDCL can be read by a 16-bit manipulation instruction.
Reset signal generation clears these registers to 0000H.
Figure 17-4. Format of Multiplication/Division Data Register C (MDCH, MDCL)
Address: F00E0H, F00E1H, F00E2H, F00E3H After reset: 0000H, 0000H R
Symbol
F00E3H
F00E2H
MDCH MDCH MDCH MDCH MDCH MDCH MDCH MDCH MDCH MDCH MDCH MDCH MDCH MDCH MDCH MDCH MDCH
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Symbol
F00E1H
F00E0H
MDCL
MDCL MDCL MDCL MDCL MDCL MDCL MDCL MDCL MDCL MDCL MDCL MDCL MDCL MDCL MDCL MDCL
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Caution The MDCH and MDCL values read during division operation processing (while the
multiplication/division control register (MDUC) is 81H) will not be guaranteed.
Table 17-4. Functions of MDCH and MDCL During Operation Execution
DIVMODE
0
1
Operation Mode
Multiplication mode
Division mode
Setting
−
−
Operation Result
−
MDCH: Remainder (higher 16 bits)
MDCL: Remainder (lower 16 bits)
Remark DIVMODE: Bit 7 of the multiplication/division control register (MDUC)
The register configuration differs between when multiplication is executed and when division is executed, as follows.
• Register configuration during multiplication
<Multiplier A> <Multiplier B>
<Product>
MDAL (bits 15 to 0) × MDAH (bits 15 to 0) = [MDBH (bits 15 to 0), MDBL (bits 15 to 0)]
• Register configuration during division
<Dividend>
<Divisor>
[MDAH (bits 15 to 0), MDAL (bits 15 to 0)] ÷ [MDBH (bits 15 to 0), MDBL (bits 15 to 0)] =
<Quotient>
<Remainder>
[MDAH (bits 15 to 0), MDAL (bits 15 to 0)] ⋅⋅⋅ [MDCH (bits 15 to 0), MDCL (bits 15 to 0)]
R01UH0004EJ0501 Rev.5.01
712
Jun 20, 2011