UPD78F1502AGK-GAK-AX Datasheet, PDF (803/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 21 STANDBY FUNCTION
(b) Release by reset signal generation
When the reset signal is generated, STOP mode is released, and then, as in the case with a normal reset
operation, the program is executed after branching to the reset vector address.
Figure 21-7. STOP Mode Release by Reset
(1) When high-speed system clock is used as CPU clock
STOP
instruction
Reset signal
Status of CPU
High-speed
system clock
(X1 oscillation)
Normal operation
(high-speed
system clock)
STOP mode
Reset
period
Reset processing
(about 2.1 to 5.8 ms)
Normal operation
(internal high-speed
oscillation clock)
Oscillates
Oscillation Oscillation
Oscillation stopped stopped stopped
Oscillates
Oscillation stabilization time
(Checked by using OSTC register)
Starting X1 oscillation is
specified by software.
(2) When internal high-speed oscillation clock is used as CPU clock
STOP
instruction
Reset signal
Status of CPU
Internal high-speed
oscillation clock
Normal operation
(internal high-speed
oscillation clock)
STOP mode
Reset
period
Oscillates
Oscillation
Oscillation stopped stopped
Reset processing
(about 2.1 to 5.8 ms)
Normal operation
(internal high-speed
oscillation clock)
Oscillates
Wait for oscillation
accuracy stabilization
Remark fX: X1 clock oscillation frequency
R01UH0004EJ0501 Rev.5.01
787
Jun 20, 2011