UPD78F1502AGK-GAK-AX Datasheet, PDF (338/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 6 TIMER ARRAY UNIT
Figure 6-56. Operation Procedure When Input Signal High-/Low-Level Width Measurement Function Is Used
Software Operation
Hardware Status
TAU
default
setting
Power-off status
(Clock supply is stopped and writing to each register is
disabled.)
Sets the TAU0EN or TAU1EN bits of the PER0 register
to 1.
Power-on status. Each channel stops operating.
(Clock supply is started and writing to each register is
enabled.)
Sets the TPSp register.
Determines clock frequencies of CKp0 and CKp1.
Channel
default
setting
Sets the TMRpq register (determines operation mode of
channel).
Clears TOEpq to 0 and stops operation of TOpq.
Channel stops operating.
(Clock is supplied and some power is consumed.)
Operation Sets the TSpq bit to 1.
start
The TSpq bit automatically returns to 0 because it is a
trigger bit.
TEpq = 1, and the TIpq pin start edge detection wait
status is set.
Detects TIpq pin input count start valid edge.
Clears TCRpq to 0000H and starts counting up.
During
operation
Set value of the TDRpq register can be changed.
The TCRpq register can always be read.
The TSRpq register is not used.
Set values of TMRpq, TOMp, TOLp, TOp, and TOEp
registers cannot be changed.
When the TIpq pin start edge is detected, the counter
(TCRpq) counts up from 0000H. If a capture edge of the
TIpq pin is detected, the count value is transferred to
TDRpq and INTTMpq is generated.
If an overflow occurs at this time, the OVFpq bit of the
TSRpq register is set; if an overflow does not occur, the
OVFpq bit is cleared. TCRpq stops the count operation
until the next TIpq pin start edge is detected.
Operation The TTpq bit is set to 1.
stop
TTpq bit automatically returns to 0 because it is a
trigger bit.
TEpq = 0, and count operation stops.
TCRpq holds count value and stops.
The OVFpq bit of the TSRpq register is also held.
TAU stop
The TAU0EN or TAU1EN bits of PER0 register is cleared
to 0.
Power-off status
All circuits are initialized and SFR of each channel is
also initialized.
Remark
pq: Unit number + Channel number (only for channels provided with timer I/O pins)
78K0R/LF3: p = 0, pq = 00 to 04, 07
78K0R/LG3: p = 0, pq = 00 to 07
78K0R/LH3: p = 0, 1, pq = 00 to 07, 10 to 13
R01UH0004EJ0501 Rev.5.01
322
Jun 20, 2011