UPD78F1502AGK-GAK-AX Datasheet, PDF (611/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 15 SERIAL INTERFACE IICA
(6) IICA low-level width setting register (IICWL)
This register is used to set the low-level width of the SCL0 pin signal that is output by serial interface IICA.
The IICWL register can be set by an 8-bit memory manipulation instruction.
Set the IICWL register while operation of I²C is disabled (bit 7 (IICE) of IICA control register 0 (IICCTL0) is 0).
Reset signal generation sets this register to FFH.
Figure 15-10. Format of IICA Low-Level Width Setting Register (IICWL)
Address: F0232H After reset: FFH R/W
Symbol
7
6
5
4
3
2
1
0
IICWL
(7) IICA high-level width setting register (IICWH)
This register is used to set the high-level width of the SCL0 pin signal that is output by serial interface IICA.
The IICWH register can be set by an 8-bit memory manipulation instruction.
Set the IICWH register while operation of I²C is disabled (bit 7 (IICE) of IICA control register 0 (IICCTL0) is 0).
Reset signal generation sets this register to FFH.
Figure 15-11. Format of IICA High-Level Width Setting Register (IICWH)
Address: F0233H After reset: FFH R/W
Symbol
7
6
5
4
3
2
1
0
IICWH
Remark For how to set the transfer clock by using the IICWL and IICWH registers, see 15.4.2 Setting
transfer clock by using IICWL and IICWH registers.
(8) Port mode register 6 (PM6)
This register sets the input/output of port 6 in 1-bit units.
When using the P60/SCL0 pin as clock I/O and the P61/SDA0 pin as serial data I/O, clear PM60 and PM61, and
the output latches of P60 and P61 to 0.
Set IICE (bit 7 of IICA control register 0 (IICCTL0)) to 1 before setting the output mode because the P60/SCL0 and
P61/SDA0 pins output a low level (fixed) when IICE is 0.
PM6 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to FFH.
Figure 15-12. Format of Port Mode Register 6 (PM6)
Address: FFF26H After reset: FFH R/W
Symbol
7
6
5
4
3
2
1
PM6
1
1
1
1
1
1
PM61
0
PM60
PM6n
0
1
P6n pin I/O mode selection (n = 0, 1)
Output mode (output buffer on)
Input mode (output buffer off)
R01UH0004EJ0501 Rev.5.01
595
Jun 20, 2011