UPD78F1502AGK-GAK-AX Datasheet, PDF (987/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
Function
Details of
Function
APPENDIX C LIST OF CAUTIONS
Cautions
(15/39)
Page
Watchdog Controlling
When data is written to WDTE for the first time after reset release, the watchdog timer p.377 _†
timer
operation
is cleared in any timing regardless of the window open time, as long as the register is
written before the overflow time, and the watchdog timer starts counting again.
If the watchdog timer is cleared by writing “ACH” to WDTE, the actual overflow time p.377 _†
may be different from the overflow time set by the option byte by up to 2/fIL seconds.
The watchdog timer can be cleared immediately before the count value overflows. p.377 _†
The operation of the watchdog timer in the HALT and STOP modes differs as follows p.378 _†
depending on the set value of bit 0 (WDSTBYON) of the option byte (000C0H). (See
the table on page 378.)
If WDSTBYON = 0, the watchdog timer resumes counting after the HALT or STOP
mode is released. At this time, the counter is cleared to 0 and counting starts.
When operating with the X1 oscillation clock after releasing the STOP mode, the CPU
starts operating after the oscillation stabilization time has elapsed.
Therefore, if the period between the STOP mode release and the watchdog timer
overflow is short, an overflow occurs during the oscillation stabilization time, causing
a reset.
Consequently, set the overflow time in consideration of the oscillation stabilization
time when operating with the X1 oscillation clock and when the watchdog timer is to
be cleared after the STOP mode release by an interval interrupt.
The watchdog timer continues its operation during self-programming of the flash
p.378 _†
memory and EEPROM emulation. During processing, the interrupt acknowledge time
is delayed. Set the overflow time and window size taking this delay into
consideration.
Setting overflow The watchdog timer continues its operation during self-programming of the flash p.378 _†
time
memory and EEPROM emulation. During processing, the interrupt acknowledge time
is delayed. Set the overflow time and window size taking this delay into
consideration.
Setting window When data is written to WDTE for the first time after reset release, the watchdog p.379 _†
open period
timer is cleared in any timing regardless of the window open time, as long as the
register is written before the overflow time, and the watchdog timer starts counting
again.
The watchdog timer continues its operation during self-programming of the flash p.379 _†
memory and EEPROM emulation. During processing, the interrupt acknowledge
time is delayed. Set the overflow time and window size taking this delay into
consideration.
When bit 0 (WDSTBYON) of the option byte (000C0H) = 0, the window open period p.379 _†
is 100% regardless of the values of WINDOW1 and WINDOW0.
R01UH0004EJ0501 Rev.5.01
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Jun 20, 2011