UPD78F1502AGK-GAK-AX Datasheet, PDF (993/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
Function
Details of
Function
APPENDIX C LIST OF CAUTIONS
Cautions
(21/39)
Page
Voltage ADVRC: A/D
During voltage reference operation, be sure to connect a tantalum capacitor p.436 _†
reference reference
(capacitance: 10 μF±30 %, ESR: 2 Ω (max.), ESL: 10 nH (max.)) and a ceramic
voltage control capacitor (capacitance: 0.1 μF±30 %, ESR: 2 Ω (max.), ESL: 10 nH (max.)) to the
register
VREFOUT/AVREFP pin for stabilizing the reference voltage. Furthermore, do not apply
a voltage from the VREFOUT/AVREFP pin during voltage reference operation.
To use voltage reference output (VREFOUT) to the positive reference voltage of the A/D p.436 _†
converter (ADREFP) and the positive reference voltage of the the D/A converter
(DAREFP), be sure to set VRON to 1 after setting VRSEL to 1.
Rewriting DACSWn (n = 0, 1) during A/D conversion is prohibited when both the p.437 _†
positive reference voltage of the A/D converter (ADREFP) and the positive reference
voltage fo the D/A converter (DAREFP) are the voltage reference output (VREFOUT)
(VRSEL = 1 and DAREF = 1). Rewrite it when conversion operation is stopped
(ADCS = 0).
Do not change the output voltage of the reference voltage by using VRGV during the p.437 _†
voltage reference operation (VRON = 1).
VREFOUT pin
The VREFOUT output voltage can be used only as the positive reference voltage of the p.437 _†
internal A/D and D/A converters of the microcontroller. Do not connect an external
circuit other than a tantalum capacitor (capacitance: 10 μF±30 %, ESR: 2 Ω (max.),
ESL: 10 nH (max.)) and a ceramic capacitor (capacitance: 0.1 μF±30 %, ESR: 2 Ω
(max.), ESL: 10 nH (max.)) to the VREFOUT pin for stabilizing the reference voltage.
Configuration SDRmn: Lower Be sure to clear bit 8 to “0”.
p.445 _†
of serial
8 bits of the
array unit serial data
register mn
PER0:
When setting serial array unit m, be sure to set SAUmEN to 1 first. If SAUmEN = 0, p.447 _†
Peripheral
writing to a control register of serial array unit m is ignored, and, even if the register is
enable register 0 read, only the default value is read (except for input switch control register (ISC),
noise filter enable register (NFEN0), port input mode register (PIM1, PIM7), port
output mode register (POM1, POM7, POM8), port mode registers (PM1, PM5, PM7,
PM8), and port registers (P1, P5, P7, P8)).
After setting the SAUmEN to 1, be sure to set the SPSm register after 4 or more p.447 _†
clocks have elapsed.
SPSm: Serial Be sure to clear bits 15 to 8 to “0”.
p.448 _†
clock select
After setting the SAUmEN to 1, be sure to set the SPSm register after 4 or more p.448 _†
register m
clocks have elapsed.
SMRmn: Serial Be sure to clear bits 13 to 9, 7, 4, and 3 to “0”. Be sure to set bit 5 to “1”.
p.449 _†
mode register
mn
SCRmn: Serial Be sure to clear bits 3, 6, and 11 to “0”. Be sure to set bit 2 to “1”.
pp.451 _†
communication
operation setting
to 453
register mn
SDRmn: Serial Be sure to clear bit 8 to “0”.
p.454 _†
data register mn Setting SDRmn[15:9] = (0000000B, 0000001B) is prohibited when UART is used. p.454 _†
Setting SDRmn[15:9] = 0000000B is prohibited when the simplified I²C is used. Set p.454 †
SDRmn[15:9] to 0000001B or greater.
R01UH0004EJ0501 Rev.5.01
977
Jun 20, 2011