UPD78F1502AGK-GAK-AX Datasheet, PDF (776/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 19 INTERRUPT FUNCTIONS
Figure 19-10. Format of Priority Specification Flag Registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H,
PR10L, PR10H, PR11L, PR11H, PR12L, PR12H) (78K0R/LH3) (2/2)
Address: FFFEBH After reset: FFH R/W
Symbol
<7>
<6>
<5>
PR01H TMPR004 SREPR02 SRPR02
<4>
CSIPR020
IICPR020
STPR02
<3>
KRPR0
<2>
RTCIPR0
<1>
RTCPR0
<0>
ADPR0
Address: FFFEFH After reset: FFH R/W
Symbol
<7>
<6>
<5>
PR11H TMPR104 SREPR12 SRPR12
<4>
CSIPR120
IICPR120
STPR12
<3>
KRPR1
<2>
RTCIPR1
<1>
RTCPR1
<0>
ADPR1
Address: FFFD8H After reset: FFH R/W
Symbol
<7>
<6>
<5>
PR02L
PPR010 PPR09
PPR08
<4>
PPR07
<3>
PPR06
<2>
<1>
<0>
TMPR007 TMPR006 TMPR005
Address: FFFDCH After reset: FFH R/W
Symbol
<7>
<6>
<5>
PR12L
PPR110 PPR19
PPR18
<4>
PPR17
<3>
PPR16
<2>
<1>
<0>
TMPR107 TMPR106 TMPR105
Address: FFFD9H After reset: FFH R/W
Symbol
7
6
<5>
PR02H
1
1
MDPR0
<4>
<3>
<2>
<1>
TMPR013 TMPR012 TMPR011 TMPR010
<0>
PPR011
Address: FFFDDH After reset: FFH R/W
Symbol
7
6
<5>
PR12H
1
1
MDPR1
<4>
<3>
<2>
<1>
TMPR113 TMPR112 TMPR111 TMPR110
<0>
PPR111
XXPR1X
0
0
1
1
XXPR0X
0
1
0
1
Priority level selection
Specify level 0 (high priority level)
Specify level 1
Specify level 2
Specify level 3 (low priority level)
Caution Be sure to set bits 6, 7 of PR02H and PR12H to 1.
(4) External interrupt rising edge enable registers (EGP0, EGP1), external interrupt falling edge enable registers
(EGN0, EGN1)
These registers specify the valid edge for INTP0 to INTP11.
EGP0, EGP1, EGN0, and EGN1 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
R01UH0004EJ0501 Rev.5.01
760
Jun 20, 2011