UPD78F1502AGK-GAK-AX Datasheet, PDF (797/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 21 STANDBY FUNCTION
(b) Release by reset signal generation
When the reset signal is generated, HALT mode is released, and then, as in the case with a normal reset
operation, the program is executed after branching to the reset vector address.
Figure 21-4. HALT Mode Release by Reset
(1) When high-speed system clock is used as CPU clock
HALT
instruction
Reset signal
Status of CPU
High-speed
system clock
(X1 oscillation)
Normal operation
(high-speed
system clock)
HALT mode
Oscillates
Reset
period
Reset processing
(about 2.1 to 5.8 ms)
Normal operation
(internal high-speed
oscillation clock)
Oscillation Oscillation
stopped stopped
Oscillates
Oscillation stabilization time
(2⁸/fX to 2¹¹/fX, 2¹³/fX, 2¹⁵/fX, 2¹⁷/fX, 2¹⁸/fX)
Starting X1 oscillation is
specified by software.
(2) When internal high-speed oscillation clock or 20 MHz internal
high-speed oscillation clock is used as CPU clock
HALT
instruction
Reset signal
Status of CPU
Normal operation
(internal high-speed
oscillation clock or
20 MHz internal
high-speed
oscillation clock)
HALT mode
Internal high-speed oscillation clock
or 20 MHz internal high-speed
oscillation clock
Oscillates
Reset
period
Oscillation
stopped
Reset processing
(about 2.1 to 5.8 ms)
Normal operation
(internal high-speed
oscillation clock)
Oscillates
Wait for oscillation
accuracy stabilization
(3) When subsystem clock is used as CPU clock
HALT
instruction
Reset signal
Normal operation
Status of CPU (subsystem clock)
HALT mode
Subsystem clock
(XT1 oscillation)
Oscillates
Reset
period
Reset processing
(about 2.1 to 5.8 ms)
Normal operation mode
(internal high-speed
oscillation clock)
Oscillation Oscillation
stopped stopped Oscillates
Starting XT1 oscillation is
specified by software.
Remark fX: X1 clock oscillation frequency
R01UH0004EJ0501 Rev.5.01
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Jun 20, 2011